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In our work we present statistical methods and new memory array analysis approaches for decomposition and assessment of contributors to the Vth distribution widening. There, cell threshold voltage characteristics along bitlines and wordlines are considered as well as hidden systematic effects by convolutional analysis. Based on investigations on sub-50 nm floating gate NAND memory arrays we demonstrate...
For the first time a stochastic model of the program operation in NAND flash memories is proposed. The model incorporates intrinsic noise effects on the threshold voltage (Vth) distribution of the memory cells in incremental step pulse programming (ISPP) schemes. An excellent agreement of the model with experimental data at 48 nm ground rule is demonstrated. This model for cell-system interaction...
Floating gate NAND flash memory arrays with 64 cells per string and high-k inter poly dielectric have been fabricated on a 36 nm ground rule using sub-lithographic patterning techniques (pitch fragmentation). The influence of pitch fragmentation inherent critical dimension variations on the electrical parameters of the memory cells such as string saturation current, initial threshold voltage, and...
A 63nm Twin Flash memory cell with a size of 0.0225 mum2 / 2 (4) bits is presented. The cell is proposed for data Flash products with 4 to 16 Gbit densities. To achieve small cell areas, a buried bit line and an aggressive gate length of ~100 nm are the key features of this 63nm Twin Flash cell. The cell is well capable of 2 and 4 bit operation.
Analyzing the electrical degradation of modern flash memory cells by conventional C-Vor charge pumping techniques is hardly possible due to the extremely small gate area. However, 1/f noise measurements can be done since low frequency 1/f noise in the range around 1 Hz produced by stress-generated oxide traps strongly increases in MOSFETs with shrinking area. Here we show that measurements of the...
Nitride based, localized charge trapping storage flash memory devices with a SONOS stack get increasingly interest due to some advantages compared to conventional floating gate memory devices (Eitan et al., 2000). One of these is the ability to store multi bits in one single cell. There are several previous attempts to simulate and to measure the lateral extend of the localized charges. For the first...
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