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This paper presents a process in which a 55 V-class of power devices is added to baseline 0.25 um 2.5 V/5 V/ 20 V CMOS technology by forming asymmetric extended-drain device structures in which an inverted well design concept is utilized to form an extended-drain dielectric region. The RsP-BVdS figure-of-merit is consistent with best-in-class (0.65 mOhm cm2 / 70 V NMOS, 1.60 mOhm cm2 / 70 V PMOS),...
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