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This work presents a 32 nm SOI CMOS technology featuring high-k/metal gate and an SRAM cell size of 0.149 mum2. Vmin operation down to 0.6 V in a 16 Mb SRAM array test vehicle has been demonstrated. Aggressive ground rules are achieved with 193 nm immersion lithography. High performance is enabled by high-k/metal gate plus innovation on strained silicon elements including embedded SiGe and dual stress...
We present a 45-nm SOI CMOS technology that features: i) aggressive ground-rule (GR) scaling enabled by 1.2NA/193nm immersion lithography, ii) high-performance FET response enabled by the integration of multiple advanced strain and activation techniques, iii) a functional SRAM with cell size of 0.37mum2, and iv) a porous low-k (k=2.4) dielectric for minimized back-end wiring delay. The list of FET-specific...
We have investigated the impact of laser spike anneal (LSA) on the performance of ultra-thin SOI MOSFETs. LSA was found to significantly reduce the parasitic external resistance in UTSOI devices. Reduced external resistance in conjunction with improved gate activation resulted in a substantial improvement in nFET performance. A conventional spike RTA followed by LSA at 1300C enhances nFET drive current,...
We report for the first time, the effect of stress memorization (SM), and the combined effects of SM and dual stress liner (DSL) on high performance fully-depleted ultra-thin channel devices with a raised source/drain architecture and channel thickness of 18nm. SM results in significant drive current and mobility enhancement, comparable to that obtained using the DSL approach. Stress transfer to the...
A high performance 65 nm SOI CMOS technology is presented. Dual stress liner (DSL), embedded SiGe, and stress memorization techniques are utilized to enhance transistor speed. Advanced-low-K BEOL for this technology features 10 wiring levels with a novel K=2.75 film in selected levels. This film is a SiCOH-based dielectric optimized for stress to enable integration for enhanced performance. The resulting...
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