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This article presents a router, called Rover II, for via-configurable structured ASIC with mixed standard cells and relocatable IPs. Rover II extends the work of Rover and incorporates a porting of NTHU-Route 2.0 and NCTU-GR global routers. Experimental results show that Rover II can successfully route a via-configurable structured ASIC with standard cells and IPs under different routing fabrics....
Memory blocks in a structured ASIC are normally pre-customized with fixed sizes and placed at predefined locations. The number of memory blocks is also pre-determined. This imposes a stringent limitation on the use of memory blocks, often creating a situation of either insufficient capacity or considerable waste. To remove this limitation, in this paper we propose a method to create relocatable and...
This paper presents a simple method for design and analysis of a via-configurable routing fabric formed by an array of routing fabric blocks (RFBs). The method simply probes into an RFB rather than resorts to full-chip routing to collect some statistics for a metric used to qualify the RFB. We find that the trade-off between wire length and via count is a good metric. This metric has been validated...
In this paper, we propose a clock routing algorithm for structured ASICs using predefined yet via-configurable metal wires. Our algorithm has many distinct features implemented to address the specific problems encountered by the tasks of creating tapping points and performing wire snaking. We also present an approach to merging two subtrees without exacerbating the skew of a merged tree. Experimental...
Structured ASIC has been introduced to bridge the power, performance, area and design cost gaps between ASIC and FPGA. As technology scales, leakage power consumption becomes a serious problem. Among the leakage power reduction techniques, power gating is commonly used to disconnect idle logic blocks from power network to curtail sub-threshold leakage. In this paper, we apply power gating to structured...
Structured ASIC is a well-developed technology that enables a shorter design Turn-Around-Time (TAT) as well as less non-recurring-engineering (NRE) cost for very deep submicron designs. Since 2003, Faraday technology has developed its own structured ASIC solutions. Based on its own competitive technology architecture, Faraday has proposed platform-based SoC solutions and realized more than 100 customer...
In this paper, we investigate via-configurable logic block (VCLB) architectures of different granularities and logic styles for standard-cell like structured ASIC. VCLB granularity ranges from a few to tens of transistors. Logic styles include those realized using series-parallel transistors and look-up table. VCLBs are designed to enable a standard cell design style so that we can establish a structured...
A structured ASIC has some arrays of pre-fabricated yet configurable logic blocks (CLBs) with/without a regular routing fabric. In this paper, we propose a standard cell like via-configurable logic block (VCLB). We design a 0.18 um standard cell library based on our VCLB and establish a design flow using as many commercial tools as possible. We also propose a method to evaluate the viability of a...
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