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We report pulsed high-k gate dielectric breakdown in various configurations emulating ESD stress in real input/output circuits. The stress on the receiver is of greater concern than is stress on the driver due to different gate oxide areas under stress. Methods to improve pad voltage tolerance for gate oxide breakdown are proposed.
We present a successfully implemented ESD design automation framework that evaluates and verifies the ESD protection methodology at all stages of a standard integrated circuit design flow. The tools used at each step of the flow and sample results showing excellent correlation to hardware test data is presented.
We present a novel multi-RC-triggered MOSFET-based power clamp with up to 70% trigger circuit area reduction and improved transient HBM, MM, and CDM ESD clamping performance. A three-stage RC-trigger circuit design gives a 300ns self-shutdown time during power-up for mistrigger leakage current control and an improved mistrigger immunity down to 1µs power-up rise time. TLP and HBM hardware characterization...
We present a novel RC-triggered, MOSFET-based power clamp for on-chip ESD protection. The cascaded PFET feedback technique is introduced. As with other feedback techniques, only a very small time constant is required for the RC trigger circuit which results in reduced capacitor area and reduced leakage at power-up. If mistriggering occurs, it is self-corrected with this dynamic feedback technique.
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