The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Parabolic motion cameras are used to obtain better deblurring results of scenes with multiple moving objects. The core of its deblurring process is Iterative Re-weighted Least Squares (IRLS) method. In this paper, we design a hardware accelerator for IRLS flow. The ASIC chip is implemented using TSMC 90 nm technology. It is capable of deblurring a 640 × 480 image captured by a parabolic camera with...
Next-generation sequencing (NGS) has been widely applied to biological and medical researches for its efficient production of DNA short reads nowadays. Among various applications, de novo sequence assembly is a technique using NGS short reads to obtain a whole genome with no reference. To make assembly results accurate, it is a common practice to filter out low-quality data at the early stage of the...
The pixel shading stage determines substantial shading effects in a programmable graphics pipeline. Owing to the demanding program complexity, the pixel shading stage dominates the rendering performance. In this paper, a configurable pixel shader reduction technique is proposed to enhance the performance for mobile GPUs. Using the developed shading approach, the shading granularity can be configured...
A 172.6mW 43.8GFLOPS energy-efficient scalable eight-core 3D graphics processor is designed and implemented for mobile multimedia applications. It is fabricated in 65nm CMOS technology with core size of 7.56mm2. The buffer bridged scheduler, energy efficient transaction technique and approximated rendering scheme are proposed to efficiently utilize energy to deliver excessive graphics rendering performance...
In this paper we propose a router-sharing architecture for 3D NoC which outperforms existing 3D NoC designs under thermal impacts. According to thermal simulations, in conventional designs, the routers on the top layers far from the heat sink have to be disabled frequently to avoid thermal emergency. Therefore, the proposed architecture removes all routers on the top layers and uses only buses to...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.