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This study reported an integrated microfluidic system for automating multiplex detection of allergy microarrays. Allergy has become a common disease worldwide. However, detection for allergy on microarrays requires tedious manual operation, well-trained technicians and a relatively labor-intensive process. In this study, an integrated microfluidic system combining the microfluidic techniques and the...
Diode string was used as the effective on-chip electrostatic discharge (ESD) protection device. To reduce the leakage current and the layout area, an area-efficient and low-leakage diode string is proposed in this paper. The standard steps of P− implantation and silicide blocking in CMOS process are used in this design to realize the proposed diode string with stacked P−/N+ diodes. The test devices...
In this paper, we presents the design of a hardware temporal multi-threading architecture for a Java processor. The Java virtual machine (JVM) model is a stack machine where the process state is the snapshot of the Java stack. If the runtime stack is stored (or cached) in on-chip memory for performance reasons, the backup and restoration of the Java runtime stacks for context switching would be expensive...
To verify system-wide properties on SoC designs in Constrained Random Verification (CRV), the default set of constraints to generate patterns could be overridden frequently through the complex testbench. It usually results in the degradation of pattern generation speed because of low hit-rate problems. In this paper, we propose a technique to preprocess the solution space under each constraint set...
Generally speaking, the dependency data compression is very useful for Intellectual Property (IP) cores and SoC. We consider the shift-in power and compression ratio in low-cost ATE environment. We propose new compression architecture with fixed length for running ones. We suppose that the ATE has not repeated function and synchronization signal. In the results, when the complexity of VLSI circuit...
In this paper, new compression architecture is proposed for multiple scan-chains. We use buffers to hold back data, and use read enable signals to filter useless data. We use only four extra channels and less hardware for largest ISCAS'89 circuits to reduce test data volume and shift-in power. The average of peak/WTC shift-in turns to 3x/6.6x, after comparing (Wang and Chakrabarty, 2008) and our method...
Test access mechanism (TAM) and testing schedule for system-on-chip (SOC) are challenging problems. Testing schedule must be effective to minimize testing time, under the constraint of test resources. This paper presents a new method based on generalized rectangle packing, as two-dimensional packing. A core cuts into many pieces and utilizes the design of reconfigurable core wrappers, and is dynamic...
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