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A new design scheme intended to improve the performance of true single-phase clocked (TSPC) dual modulus prescalers is presented. Two branches of TSPC D flip-flops are merged to reduce both power and device count. An HSPICE simulation of the proposed scheme demonstrates the highest power efficiency and best power–delay product among the referenced designs.
Two novel structures for explicit-pulsed flip-flops are proposed in this paper. The charging and discharging time are greatly reduced due to the lower capacitive load of interval nodes in the new structures, and the short circuit power consumption is diminished by overcoming the race problem as well. Simulation results also indicate the new structures are ideal for high-speed and low-power digital...
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