The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
The silicon nanowire MOSFET (SNWT) with gate-all-around (GAA) architecture has exhibited great potential in high-performance nano-electronics applications. However, line-edge roughness (LER) induced by lithography and etching processes has become a critical concern for decananometer MOSFETs, because it does not scale accordingly with line widths. Especially, the LER of nanowires, which contains two...
By using combined gate current and drain current random telegraph signal noise (Ig-Id RTS) technique, both electron and hole traps within the gate stack of silicon nanowire transistors (SNWTs) with TiN metal gates are experimentally studied in this paper. For the first time, Ig RTS is observed in p-SNWTs, which originated from electron traps that are induced by multiple crystal orientations of the...
Impacts of electron trapping/detrapping on the negative bias temperature instability (NBTI) characteristics in silicon nanowire transistors (SNWTs) with metal gates are experimentally studied in this paper. It is demonstrated that large amounts of as-grown defects, including both electron traps and hole traps, are induced by nanowire structure due to multiple surface crystal orientations of the cylinder...
In this paper, experimental studies on the carrier transport in silicon nanowire transistors (SNWTs) are reported, demonstrating their great potential as an alternative device structure for near-ballistic transport from top-down approach. Both ballistic efficiency and apparent mobility were characterized. A modified experimental extraction methodology for SNWTs is proposed, which takes into account...
In this paper, the analog/RF performance of Si nanowire transistors (SNWTs) and the impact of process variation are investigated for the first time. Analog/RF figures of merit of SNWTs are studied, including transconductance efficiency gm/Id, intrinsic gain gm/gd, cutoff frequency ft , and maximum oscillation frequency fmax. The results indicate that SNWTs exhibit superior intrinsic RF scaling capability...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.