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For the past 30 years, plasma etching technology has led in the efforts to shrink the pattern size of ultra-large-scale integrated (ULSI) devices. However, inherent problems in the plasma processes, such as charge buildup and UV photon radiation, limit the etching performance for nanoscale devices. To overcome these problems and fabricate sub-10-nm devices in practice, neutral-beam etching has been...
Our newly developed neutral beam (NB) etching accomplished the damage-free (defect-free and smooth surface) fabrication of high aspect rectangular Si-fins for the first time. The fabricated FinFETs realized higher device performance (higher electron mobility) than that using a conventional reactive ion etching. The improved mobility is well explained by the NB etched atomically-flat surface. Our new...
We present the FinFET process integration technology including improved sidewall transfer (SWT) process applicable to both fins and gates. Using this process, the uniform electrical characteristics of the ultra-small FinFETs of 15nm gate length and 10 nm fin width have been demonstrated. A new process technique for the selective gate sidewall spacer formation (spacer formation only on the gate sidewall,...
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