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As the SIMD width of modern microprocessors has been widening for keeping up with the computational demand for HPC systems, recently the vector architecture comes back to spotlight. Besides, a modern vector architecture that has been keeping a large SIMD width and a high B/F ratio has survived and evolved in the HPC community. In this paper, to clarify the potential of the modern vector architecture,...
Modern memory systems are equipped with multiple channels to achieve a higher memory bandwidth. Since the multi-channel memory system focuses on achieving a high memory bandwidth, data are allocated to all the channels. Hence, when the memory system is accessed, all the channels are activated until the next DRAM refresh starts. Therefore, when executing compute-intensive applications that do not need...
Aiming at improving the energy efficiency of 3D-stacked memory subsystems, this paper proposes a power-aware last level cache (LLC) control mechanism. The proposed mechanism switches enabling/disabling the LLC according to application characteristics and the power efficiency of the memory subsystems. Evaluation results show that the proposed mechanism improves the power efficiency of 3D-stacked memory...
Since recent scientific and engineering simulations require heavy computations with large volumes of data, Highperformance Computing (HPC) systems need a high computational capability with a large memory capacity. Most recent HPC systems adopt a parallel processing architecture, where the computational capability of the processors is high, but the performance of the memory system is constrained. The...
DRAM-based main memories are energy-hungry components of modern computer systems. Since accesses to DRAM need a complex protocol, the performance of an address-mapping scheme that decides physical locations of data based on physical addresses has a big impact on energy consumption. To improve the energy efficiency, this paper proposes a mechanism that dynamically selects an appropriate address-mapping...
Since deep-submicron process technologies induce soft errors, advanced computing systems face a low dependability problem. Checkpointing, which copies data required for continuing the program execution as a backup, is expected as a promising approach to keeping a high dependability. However, checkpointing causes additional memory accesses, which cause performance and energy overheads. To reduce these...
The Improved Penalty Avoiding Rational Policy Making algorithm (IPARP) that can learn by a reward and a penalty. IPARP aims to find penalty rules that have a high possibility to receive a penalty. Though IPARP is effective in many cases, it needs many trial-and-error searches due to memory constraints. In this paper, a propagation algorithm of the Expected Failure Probability (EFP) is proposed to...
Although modern SIMD extensions enable to improve the performance of MMAs, the limited parallel-processing capability and low memory bandwidth are their drawbacks to execute next generation MMAs. This paper proposes a novel media-oriented vector architectural extension (MVPX) to aim at accelerating a wide range of next generation MMAs. MVPX consists of an out-of-order vector processing mechanism (OVPM)...
To realize a high computational efficiency, a 3-D stacked chip multi-vector processor (CMVP) has been proposed. However, the 3-D stacked CMVP has not been evaluated well in terms of energy consumption. Therefore, to clarify the potential of the 3-D stacked CMVP, this paper evaluates and analyzes the energy consumption of the 3-D stacked CMVP using real scientific applications. Especially, this paper...
The penalty avoiding rational policy making algorithm (PARP) previously improved to save memory and cope with uncertainty, i.e., Improved PARP (IPARP). The efficiency of IPARP is influenced by threshold of a penalty rule or a penalty basis function γ significantly. In this paper, we propose a technique for learning γ. We show the effectiveness of our proposal using a soccer game task called “Keepaway”.
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