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This paper presents a very small circuit area analog-to-digital converter (ADC) for three-dimensional (3-D) stacked CMOS image processing system. To realize high-speed image sensor, we have proposed a block-parallel signal processing with 3-D stacked structure. The proposed block-parallel analog signal processing elements contains CMOS image sensor, correlated double sampling (CDS) array, and ADC...
This paper reports on a polar transmitter that is capable of 8-DPSK modulation for the Bluetooth EDR standard. It implements the second-order approximation scheme in the gain calculation of the DCO and a phase rotation-constant digital PA. It achieves DEVM of 6.1% at 0dBm output in sending 8-DPSK signal for Bluetooth EDR, drawing 35mA from a 1.2V supply and occupies 0.75χ0.75mm2.
This paper describes a non-binary SAR ADC architecture that is reconfigurable at production testing time to increase the number of chips that meet a given sampling speed specification, i.e. to improve yield. A non-binary SAR ADC can realize higher sampling rates than a comparable conventional binary SAR ADC, by using overlapping SA ranges so that any errors due to incomplete settling of the internal...
In this paper, we describe the fundamental study of the block-parallel analog signal processing elements which includes CMOS image sensor, correlated double sampling (CDS) array, and analog-to-digital converter (ADC) array. To realize high-speed image capturing sensor, we have proposed a blockparallel signal processing with three-dimensional (3-D) structure. In proposed system, one block consists...
Considering the trade-off between performance and power consumption has become significantly important in multi-core processor design. Under this situation, one promising approach is to employ a power-aware dynamic cache partitioning mechanism. This mechanism individually manages activation of each cache way, and exclusively allocates the minimum number of required ways to each thread. In the mechanism,...
Submicron single crystal-Si TFTs and a test circuit are integrated on a 320 mm ?? 400 mm ( Gen 1 ) glass substrate for the first time, by transferring devices using hydrogen exfoliation and direct bonding without adhesive. Characteristics of the NMOS-TFT is comparable with that of SOI, while PMOS-TFT shows some degradation of sub-threshold swing. Transferred CMOS show high performance and shift register...
A 2.4 GHz 0.13 μm CMOS transceiver achieving high RX sensitivity and high-quality TX signals between -40°C and +90°C is presented. A low-IF receiver and direct-conversion transmitter architecture is employed. A temperature compensated receiver chain including LNA achieves a sensitivity of -89.6 dBm even in the worst environmental condition. Linearity optimization for the transmitter chain including...
A 5 GHz MIMO direct-conversion transceiver composed of 2 transmitters (TXs) and 3 receivers (RXs) is fabricated with 0.13 mum CMOS technology. Die size is 4.56 mm times 7.7 mm. For driving 10 GHz LO signal lines of 5 mm length for both TXs and RXs, inductor-less low-power LO repeaters are equipped in individual LO paths. A linearized RF variable gain amplifier is proposed for low power operation....
A second-order multibit switched-capacitor (SC) complex bandpass ΔΣ AD modulator has been designed, fabricated and tested for application to low-IF receivers in wireless communication systems. We have employed two new algorithms there to improve the signal-to-noise-and-distortion (SNDR) of the modulator, (i) A complex bandpass filter with I, Q dynamic matching to reduce the mismatch influence between...
A circuit that samples an image in two dimensions and uses a resistive network to average it spatially according to a Gaussian weighting function whose width is controlled by an electronically variable resistor is described. A matrix of logarithmic photoreceptors fabricated on the surface of the IC drives currents into the nodes of a mesh consisting of appropriately ratioed positive and negative resistors...
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