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We present a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital PLL (ADPLL). It employs a MASH ΔΣ time-to-digital converter (TDC) to achieve low in-band phase noise, and a wide-tuning range digitally-controlled oscillator (DCO). Fabricated in 40nm CMOS, the ADPLL consumes 10.7 mW while outputting 1.73 to 3.38 GHz (after a ÷2 division) and achieves better than −109 dBc/Hz...
A digital phase-locked loop (DPLL) which uses a high resolution 2-dimension gated-Vernier time-to-digital converter (TDC) is presented. The shaped Vernier quantization of TDC greatly improves the in-band phase noise. Also the 2-dimension structure makes DPLL be able to process large phase errors almost without the influence of latency time. Combined with a high figure-of-merit (FOM) class-D digitally...
This paper presents a 1MHz bandwidth, ΔΣ fractional-N PLL as the frequency synthesizer for LTE. A noise cancellation path composed of a novel hybrid ΔΣ DAC with 9 output bits is incorporated into the PLL in order to cancel the out-of-band phase noise caused by the quantization error. Further, a re-timing circuit is proposed to reduce the nonlinearity in the Charge Pump and provide pulse shaping signals...
This paper presents the design of a digital PLL which uses a high resolution Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter (TDC) for low noise RF application. The TDC uses two gated ring oscillators (GRO) acting as the delay lines in an improved Vernier TDC. The already small quantization noise of the standard Vernier TDC is further first-order shaped by the GRO operation. Additionally,...
An all digital phase-locked loop (ADPLL) has been implemented in a 90-nm CMOS process. It uses a phase frequency detector (PFD) connected to two time-to-digital converters (TDC). To save power the TDCs use uneven delay time in the delay line cells. An automatic tuning bank controller selects active bank of the digitally controlled oscillator (DCO), which features three separate tuning banks. The PLL...
A 5.4 GHz digitally controlled oscillator (DCO) has been implemented in a 90-nm CMOS process. It has three different frequency control words, coarse, medium, and fine. The coarse control bank uses MIM capacitors and differential MOS switches. The other banks use MOS varactors. The phase noise was measured at the output of an on-chip divide by 2 circuit. It is -132 dBc/Hz at 3 MHz offset from the 2...
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