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The present work focuses on the microstructure of annealed damascene Cu interconnects with different trench aspect ratio and line spacing. The X-ray diffraction (XRD) and electron backscatter diffraction (EBSD) measurements are conducted on the surface of Cu interconnects after removal of the SiN layer. The experimental results show that strong {111} fibre texture exists in the Cu interconnects, and...
This paper addresses the design of the mapping tool used for the FPGA application implementation in our SRAM-based FPGAs fabricated in a 0.5 micron SOI-CMOS process. Comparing with the existing mapping tools from academia, we propose several techniques of packing and clustering to improve the technology mapping. The proposed algorithms provide a closer matching of the user logic netlist with the underlining...
Hydrostatic stress of Cu damascene interconnects were calculated by using commercial finite element software in the present work. The analytical work was performed to examine the distribution of hydrostatic stress and the effect of different low-k dielectrics and barrier materials in the Cu interconnects. The results indicate that the hydrostatic stress is strongly dependent upon different low-k dielectrics...
Due to their influence on the mechanical properties, residual stresses in thin films have become an important topic in materials science. The elastic constants are required to determine the residual stresses using X-ray diffraction method. The elastic constants of Cu thin films with ideal fibre textures were calculated using the Voigt, Reuss and Hill model in the present work. The results show that...
In this work, we propose and verify a robust dual damascene air gap architecture, which avoids the increasing complexity and cost normally associated with current multilevel air gap integration. Air gap packaging reliability was also addressed showing promising stud bonding and wire pull test results. Furthermore two solutions are proposed to solve any possible un-landed via issues, including simultaneous...
In this work, we demonstrate the capability of Ecmp to meet the 45 nm and 32 nm technology node requirements in terms of topography behavior, the related electrical spread, lithography DOF budget and ULK compatibility.
As the technology node advances into the nanometer era, via-open defects are one of the dominant failures. To improve via yield and reliability, redundant-via insertion is a highly recommended technique proposed by foundries. Traditionally, double-via insertion is performed at the post-layout stage. The increasing design complexity, however, leaves very limited space for post-layout optimization....
MOCVD TiSiN was evaluated as a barrier for Cu interconnects application. The TiSiN film was formed by SiH/sub 4/ soaking of MOCVD TiN. The TiSiN film showed improved wetting and adhesion to Cu as well as less stress hysteresis in its integration with Cu. The low stress hysteresis yields higher resistance to Cu void generation during hot storage testing. Electrical tests on DLM Cu test structures demonstrated...
Electrochemical deposition (ECD) is currently the only practical process for manufacturing Cu interconnections on silicon integrated circuits. However, this application is relatively new and some issues related to ECD defects remain to be resolved. One of the most important types of ECD defects consists of voids clustered together to form curved lines, referred to as "swirl defects". The...
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