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For faster timing closure, a parasitic extraction method is developed for the pre-route VLSI design. This method generates virtual route and estimates congestion using the placement information of standard cells, and then extract the interconnect parasitics with the pattern-library method. The techniques of generating parasitic RC tree according to the improved FLUTE algorithm, and capacitance extraction...
Rewiring is a useful technique that perturbs the logic of Look-Up Tables (LUTs) without changing the functions of circuits. This internal logic perturbation can be used to trade for critical LUT-external logic/wire removals for EDA improvements. In this paper, we design a flow of embedding the rewiring engine into routing process for FPGA improvement. In our design, we change the priorities of target...
Manufacturing hotspots are the layout patterns which cause excessive difficulties to manufacturing process. Design rules are effective at handling sizing/spacing induced hotspots, but are inadequate at dealing with topological hotspots. In wire routings, existing approaches often remove the hotspots through iteratively ripping up and rerouting one net at a time guided by litho-simulations. This procedure...
In this paper, a novel design-for-manufacture-aware detailed routing algorithm that seeks to minimize the thickness range of the chip surface after copper damascene process is proposed. The paper is based on an electroplating (ECP) and chemical mechanical polishing (CMP) model and predictors for final thickness range are abstracted. The proposed detailed routing is implemented in a W-shape multilevel...
Cell migration has been widely used in global placement for the highly efficiency in smoothing cells overlap. The current cell migration methods only locally or globally smooth the density without considering the relation between the local and the global density. Furthermore, the cells generally are treated as points with area. In this paper we present a new cell migration technique called CSAGO to...
This paper presents a new detailed router for the hierarchical field programmable gate arrays (H-FPGAs). The optimal objectives of proposed routing algorithm are improving the time consumption of routing procedure (minimizing the running time of algorithm), and at the same time make great effort to decrease the wire length and critical path delay. Initially, nets are routed sequentially according...
The technique of cell shifting has the advantage of linearly smoothing the overlap in placement. In the shifting process we should preserve the integrity of the original placement as much as possible and do less damage to the relative locations of the cells. The current cell shifting methods only locally or globally smooth the density without considering the relation between the local and the global...
Decoupling capacitance (decap) is an efficient way to reduce transient noise in on-chip power supply networks. However, excessive decap may cause more leakage power, chip resource waste, and even lead to more design iterations. In this paper, we present a novel decap-efficient placement algorithm for transient power supply noise reduction. In contrast to traditional design flow, our approach considers...
In this paper, we present a top-down global placement algorithm considering wire density uniformity for CMP variation control. The proposed algorithm is based on top-down recursive bisection framework. Wire weight balancing constraint is employed into bisection to consider wire density uniformity. A multilevel hypergraph partitioning satisfying balancing constraints on not only cell area but also...
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