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We have proposed gate-all-around Silicon nanowire MOSFET (SNWFET) on bulk Si as an ultimate transistor. Well controlled processes are used to achieve gate length (LG) of sub-10nm and narrow nanowire widths. Excellent performance with reasonable VTH and short channel immunity are achieved owing to thin nanowire channel, self-aligned gate, and GAA structure. Transistor performance with gate length of...
Hot carrier (HC) reliability of gate-all-around twin Si nanowire field effect transistor (GAA TSNWFET) is reported and discussed with respect to size and shape of nanowire channel, gate length, thickness and kind of gate dielectric in detail. Smaller nanowire channel size, shorter gate length and thinner gate oxide down to 2 nm thickness show worse hot carrier reliability. The worst VD for 10 years...
In this work, fabrication of TSNWFET on SOI with down to 25-nm TiN surrounding gate and 8-nm silicon nanowires is reported with high manufacturability and improved device reliability including reduced junction and gate leakage currents by fully eliminating the bottom parasitic channel existing in previous TSNWFET on bulk Si. And high performance is also obtained to be 1124muA/mum and 1468muA/mum at...
Gate-all-around (GAA) MOSFET with single silicon nanowire is fabricated and applied to SONOS memory as a cell transistor for NAND flash string. Driving current over 1 uA, which is sufficient to NAND string, is obtained with single nanowire of ~7 nm width. Using FN tunneling conditions, VTH window of 4.5 V and fast program/erase (P/E) speed of ~10 us are obtained, respectively. The smaller nanowire...
Strained silicon nanowire transistor with embedded SiGe (e-SG) source/drain is investigated for the first time on experiments. By compressive stress induced by e-SG, PMOS performance is improved by about 85%. <110>-oriented nanowire channel also contributes 80% PMOS performance improvement relative to <100> direction. By combination of uniaxial stress and <110> channel direction,...
The device characteristics of Si-nanowire FET (Si-NWFET) are investigated with non-equilibrium Green's function (NEGF) method. In this study, we characterize the effect of channel modulation by engineering dopant profiles, oxide thickness, and corner rounding of nanowire cross section, and suggest how to enhance the performance of Si-NWFET. Our simulation shows that the engineering of dopant profiles...
For the first time, we have successfully fabricated gate-all-around twin silicon nanowire transistor (TSNWFET) on bulk Si wafer using self-aligned damascene-gate process. With 10nm diameter nanowire, saturation currents through twin nanowires of 2.64 mA/mum, 1.11 mA/mum for n-channel TSNWFET and p-channel TSNWFET are obtained, respectively. No roll-off of threshold voltages, ~70 mV/dec. of substhreshold...
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