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An autonomously bias gated synchronous boost regulator consuming 110nA at 1V is demonstrated in 130nm CMOS. The IC generates regulated 1V output from 30mV input, starts up autonomously (battery-less) at 265mV, and regulates output ranging from 0.78V-3.3V. The peak efficiency is 83% with 10μA and 85% with 10mA load.
This paper presents a circuit implementation of a simple but accurate NMOS Vt based clamping technique to decrease the logic transition delay in an ultra low ground current comparator. In a very low current comparator the output logic delay is predominantly set by the speed of slew limited decision making nodes and hence limiting their wide swing by clamping them around the decision point is one of...
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