The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
We propose a built-in test circuit to detect resistive open defects occurring at interconnects between dies of 3D ICs. The test circuit consists of an I-V converter and a comparator of offset cancellation type. Feasibility of the tests with the circuit is examined by SPICE simulation. It is shown that resistive open defects of 5Ω and above can be detected per 240nsec under process variations of MOSs...
We have proposed a power supply circuit and an electrical interconnect test method based on charge volume supplied from the power supply circuit. We optimize the supply circuit so as for small resistive open defects that occur at interconnects among dies in 3D stacked ICs to be detected by the test method. We examine what resistive open defects can be detected with the optimized power supply circuit...
An electrical interconnect test method and a testable design method are proposed of a 3D stacked ICs made of dies in which boundary scan flip flops are not embedded in this paper. Open defects occurring at interconnects between dies designed by the testable design method are detected by the test method. In order to examine feasibility of the electrical tests, a PCB circuit is tested by the test method...
In this paper, a built-in supply current test circuit is proposed to detect open defects occurring at interconnects between dies including an IEEE 1149.1 test circuit and locate the defective interconnects in a 3D IC. Feasibility of interconnect tests with the test circuit is examined by some experiments with a prototyping IC in which the test circuit is embedded and by Spice simulation. The simulation...
An estimation method of a threshold value for electrical interconnect tests is proposed for detecting open defects at interconnects between dies in a 3D IC. Threshold values of a circuit made of our prototyping IC on a printed circuit board are derived by the estimation method. The results show us that resistive open defects whose resistance is larger than 16.1Ω can be detected with a threshold value...
An electrical test method is proposed for detecting an open defect occurring at a data bus of a 3D SRAM IC. Targeted defects are a hard open defect and a soft one in a data bus. The test method is based on supply current of the IC. There is no need to add a circuit for the test method to an original circuit. Feasibility of the tests is examined by some experiments for a circuit made of an SRAM IC...
A built-in sensor is proposed for detecting open faults in a 3D IC by means of appearance time of dynamic supply current. It is shown by Spice simulation that they can be detected with the sensor.
An estimation method of quiescent output voltage of a defective TSV is proposed at which a hard open defect occurs in a 3D IC. The method enables us to reduce the number of times of 3D electromagnetic simulation.
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.