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This paper presents a new calibration technique applicable for wide tuning range phase locked loops (PLLs) using very low gain voltage controlled oscillators (VCO). This technique uses the PLL main loop for the coarse and fine tuning of the VCO. Instead of using two loops which has been reported in previous works, in this work the VCO tuning voltage is used to calibrate the VCO switch capacitor array...
A half-rate low-power 3-tap decision feedback equalizer (DFE) was designed in 90-nm CMOS technology. An improved switched-capacitor-based summer architecture is used in the front-end sample-and-hold to speculate the first feedback tap. Other two taps are canceled using current summation technique. Further power consumption reduction is achieved by using sense-amplifier-based slicer and pass-gate multiplexer...
This paper presents an improved PMOS-based active inductor circuit suitable for output driver in wireline link transmitters. Wider tuning range and higher inductive impedance in the desired bandwidth with respect to a previous reported topology is achieved using a varactor in the active inductor architecture and modifying the feedback resistor. Using the proposed active inductor, a prototype output...
In this work the design of a low power 10-bit 100MS/s pipeline ADC is presented. Low power consumption is realized by using an optimum bit per stage resolution and also by applying the correlated level shifting (CLS) technique for the first four stages. Moreover, by obviating the need for a first stage S/H, power consumption was reduced considerably. The first stage of the pipeline has a 2.5-bit resolution,...
In this paper, a high speed latch architecture is proposed. This latch is based on a modified CML architecture, in which the tail current source is removed. To further increase the speed, shunt peaking is used. This technique can be implemented using passive or active inductors. Active inductors require smaller on-chip implementation area, but impose some drawbacks such as nonlinearity and noise....
In this paper, a high speed latch architecture is proposed. This latch is based on a modified CML architecture, in which the tail current source is removed. To further increase the speed, shunt peaking is used. This technique can be implemented using passive or active inductors. Active inductors require smaller on-chip implementation area, but impose some drawbacks such as nonlinearity and noise....
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