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The threshold voltage (Vth) instability of 4H-SiC MOSFETs was investigated using high-speed IV measurement instrument. DC stress measurement of wide time span ranging from 10−6 to 103 s without relaxation effect was conducted. The high-speed measurement allowed of dynamic ΔVth measurement under pulsed AC gate bias stress. We investigated effects of NO POA in gate oxidation process on the Vth instabilities.
In this study, we constructed a novel measurement setup with a large current rating to measure fast Id change, and evaluated the decrease in Id due to positive AC gate bias, using commercially available SiC MOSFETs. In addition, by comparing the obtained fast 7d change results with the threshold voltage (Vth) shift measured by a conventional DC gate stress test, we verified that the conventional DC...
This paper focused on the investigation of short-circuit capability and failure mechanism for the commercially available SiC trench MOSFETs. There are three failure mechanisms; (1) avalanche generation, (2) thermal runaway and (3) breakdown of gate oxide layer between gate-source electrodes by different short-circuit conditions. These are dependent upon the drain voltage and, especially in the high...
A new p-channel vertical 4H-SiC MOSFET has been successfully fabricated for the first time. Its breakdown voltage is over −730 V and the short circuit capability is 15% higher than that of 4H-SiC n-channel MOSFET. This could be a superior power device applicable for high frequency complementary inverter.
4H-SiC trench MOSFETs with novel V-groove structures have been investigated. We have fabricated trench MOSFETs with the inclined 4H-SiC{0-33-8} face [1, 2] as trench sidewalls for the channel region, resulting in a low specific on-resistance owing to the superior MOS interface properties. In addition, by using buried p+ regions inside the drift layer, a high voltage avalanche breakdown without oxide...
We have successfully developed a fabrication process for OEICs in which each device structure and performance can be optimized. We integrated InGaAs/InP HBTs and InP-passivated InGaAs pin PDs on a semi-insulating InP substrate using multi-epi growth process. For the PDs with a 60 ?m mesa diameter, the capacitance of 0.2 pF and the dark current of 0.1 nA at a reverse bias voltage of 5 V were obtained...
We have successfully fabricated mesa-type InGaAs pin PDs with InP-passivation structure monolithically integrated with resistors and capacitors. As for the PD characteristics, the capacitance of 0.19 pF and the dark current of 0.2 nA at a reverse bias voltage of 5 V are obtained. By using the MIM/MIS stacked structure in the capacitors, a large capacitance of 91 pF is obtained on a chip area of 440...
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