The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
A direct high-k/Si gate stack has been proposed for gate oxide scaling. With LaCe-silicate, an EOT of 0.64 nm with an average dielectric constant (kav) of 17.4 has been obtained and an extremely low gate leakage current (Jg) of 0.65 A/cm2. The flatband voltage (Vfb) can be controlled by the compositional ratio of La in the LaCe-silicate layer. Furthermore, incorporation of Ge atom into the silicate...
Although the mutually complementary network of wired and wireless was studied as an object for home houses and the result was got, adaptation evaluation was tried for it to small-scale buildings, such as a school building, this time. Consequently, it found out that the mutually complementary network of wired and wireless had the possibility of adaptation also at a small-scale building. In the home...
We have clarified that, in a metal/high-k gate stack, as well as the variability introduced by random dopant fluctuations (RDF), the threshold voltage variability (TVV) is attributable to the crystal structure and grain size in the metal gate. We have successfully eliminated this additional factor by reducing the grain size in the metal gate. We demonstrated that the incorporation of C into TiN metal...
We have found that effective work functions of high-work function gate metals (p-metals) become small and Fermi level pinning of gate metals occurs after high temperature treatment as the same in the case in p+poly-Si gates. On the contrary, intrinsic hybridization between metal and high-k wave function at the interface is crucial factor to determine effective work function of gate metals after low...
A laminate design technology of metal gates is proposed to improve FET characteristics regardless of EOT and gate dielectric material. The laminated metal gate structures are basically composed of low-Rs(sheet resistance) metal/ WF(work-function)-lowering layer/ WFM(WF determining metal). A thin WFM (~2 nm) laminated by the Si-based WF-lowering layer such as poly-Si or TaSiN brings an additional benefit...
We have investigated the time dependent dielectric breakdown (TDDB) characteristics for a high-k/metal gate pMOSFET under inversion stress. We found that electrons, injected from the cathode, being minority carriers in the gate leakage current play an important role in determining TDDB lifetime and found that the presence of oxygen vacancies in HfSiON determine the electron current mechanism in HfSiON...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.