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In this paper, we present a designed single Magnetic Tunnel Junction (MTJ) cell and a single switching transistor (1T-1MTJ) bitcell based 8Mb 64 I/O Spin-Transfer-Torque Magnetic RAM (STT-MRAM). Novel 3-Section Symmetric Reference Structure and high-gain Single-stage cross-coupled Sense Amplifier (SA) are implemented. The developed chip has about 40% decreased area and power consumption when compared...
Conventional patterning techniques, such as self-aligned double patterning (SADP) and litho-etch-litho-etch (LELE), have paved the way for the extreme ultraviolet (EUV) technology that aims to reduce the photomask steps [1,2]. EUV adds the extreme scaling to the high-performance of FinFET technology, thus opening up new opportunities for system-on-chip designers: delivering power, performance, and...
Two 128 Mb 6T SRAM test chips are implemented in a 10 nm FinFET technology. A 0.040 $\mu \text{m}^{2}$ 6T SRAM bitcell is designed for high density (HD), and 0.049 $\mu \text{m}^{2}$ for high performance (HP). The various SRAM assist schemes are explored to evaluate the power, performance, and area (PPA) gain, and the figure-of-merit (FOM) is induced by the minimum operating voltage ($V_{\mathrm{ MIN}}$ ...
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