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The advent of many-core system-on-chips (SoC) will involve new scalable hardware/software mechanisms that can efficiently utilize the abundance of interconnected processing elements found in these SoCs. These trends will have a great impact on the strategies for testing the systems and improving their reliability by exploiting system's re-configurability to achieve graceful degradation of system's...
The current trend of aggressive technology scaling results in a decrease in system's reliability. This motivates investigation of fault-resilient architectures which provide graceful degradation of system's functionality. In this paper, three novel fault-resilient Network-on-Chip (NoC) router architectures are proposed. These architectures, exploit the regularity of the router and reallocate available...
Routing algorithms play an important role in Network-on-Chip (NoC) based System-on-Chips. Turn model based routing disallows some of the turns in order to avoid deadlock, while providing partial adaptivity. In this paper, all 2D uniform turn models are examined for deadlock freeness and connectivity; 50 deadlock free turn models are extracted that provide full connectivity in the network. An extended...
With the scaling of silicon technology beyond the sub-micron domain, the probability of the system being exposed to different sources of faults increases. Manifestation of new defects during system's run-time, necessitates the need for a mechanism providing cost-effective online fault detection which performs concurrently with the circuit's normal operation and has low area overhead and high fault...
Due to the ongoing miniaturization of silicon technology beyond the sub-micron domain and the trend of integrating ever more components on a single chip, the Network-on-Chip (NoC) paradigm has emerged to address the scalability and performance shortcomings of bus-based interconnects. As the feature size shrinks, the system gets much more susceptible to faults caused by wear-out and environmental effects...
Face recognition is an important biometric tool due to contact independence. In real time scenarios such as criminal record databases, it is vital to provide the user with high accuracy results in reasonable time. Compared to the software counter parts, the existing hardware solutions on FPGAs provide higher accuracy. However, such systems are not scalable due to high resource utilization (i.e. number...
The susceptibility of on-chip communication links and on-chip routers to faults has guided the research towards focusing on fault-tolerance aspects of 2D and 3D Network-on- Chips (NoCs). In this paper, we propose Logic-Based Distributed Routing for 3D NoCs (LBDR3D), a scalable, re-configurable and fault-tolerant mechanism, which utilizes only two virtual channels for implementing any deadlock-free...
In this paper, an open-source framework for task deployment of mixed-critical and non-critical applications under dependability constraints in Network-on-Chip (NoC) based systems is introduced. This system level design space exploration is guided by a System Health Monitoring Unit which keeps a holistic view of system health status. The framework supports task clustering, mapping and scheduling of...
This paper describes experiences obtained conducting the “Embedded Systems Design” course at Tallinn University of Technology. After introductory lab tutorials, a complex Smart House project has been provided to the students. The students had to complete the project in a Start-up Company style environment, which demands planning, good teamwork, solid theoretical background, down to the ability to...
The deployment of mixed-criticality applications on NoC (Network-on-Chip)-based MPSoC (Multiprocessor System-on-Chip) platforms requires a stringent protection of the communication and processing resources being utilized by hard-real-time parts of the the application in order to avoid interference of less critical application parts. In this contribution we present an approach for encapsulation of...
Remote laboratories are becoming a popular practice for undergraduate and graduate engineering laboratories. The remote laboratories enable students to access lab facilities out of the official laboratory time and automatically see the results without presence of the laboratory assistants. This paper presents an ad hoc, interactive and cost-efficient remote laboratory framework that has been designed...
This paper presents an overview of teaching hardware description languages (HDL) at Tallinn University of Technology (TUT). The structure of the course was modified by change of the approach to ground up learning through practical exercises. Different techniques to increase motivates of the students were introduced. These changes and their motivations are described in this paper. The course is taught...
In order to be able to handle an arbitrary amount of static communication segment faults in NoC-based MPSoCs, a flexible fault tolerance mechanism has to be applied. In this contribution, we present a flexible and scalable approach for fault-tolerance in NoCs, which - in contrast to existing circumvention techniques - can in principle handle any number of static faults in the routing network. It doesn't...
Mapping algorithms on CGRAs can lead to an inefficient implementation and hardware under-utilization if there is a mismatch between the granularity of reconfigurable processing unit and the algorithm. In this paper, we introduce a tool that takes the hardware configuration of a set of applications, identifies the unused parts of the CGRA, and let the user sweep the design space from fully programmable...
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