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While 3D integrated circuits provide many security advantages, one disadvantage is the insertion of a Trojan die into the stack. In this paper, we explore a technique to detect an extra die through delay analysis.
We propose an architecture for an FPGA-based tester for a 3D stacked IC. Our design exploits the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns at a high bandwidth, reducing the FPGA resources required and often reducing scan shift toggling. The proposed approach and its advantages can generally also be applied to 2.5D multi-die circuits...
3-D die-stacks hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3-D stack are leading to yield issues and slowing the large scale manufacturing of these devices. In many cases, a single defective die will kill the entire stack. To help mitigate this issue, we explore the possibility of repairing a stack that contains a defective die by utilizing...
3D stacked integrated circuits hold great promise for increasing system performance, but difficulties in testing dies and assembling a 3D stack are leading to yield issues and slowing the large scale manufacture of these devices. We propose helping to mitigate these issues by repairing the stack with programmable logic in FPGAs that have already been included in the stack for other purposes. Specifically,...
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