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Transition detectors have been widely employed for online error and metastability detection, including in Better-Than-Worst-Case (BTWC) timing design of microprocessors that are designed to allow occasional timing errors. In such applications, the area overhead introduced by the transition detectors is a major concern because they may need to be incorporated in almost all the flip-flops in a large...
Better-than-worst-case timing design methodologies aim at increasing throughput by speeding up the clock to the point where circuit timing margins are reduced to zero and even beyond. In low power designs such as Razor, this efficiency improvement is translated into power savings at a fixed operational clock rate through adaptive and dynamic voltage scaling. The main challenge in such designs is the...
Better-than-worst-case timing designs such as Razor introduce shadow flip-flops triggered by a delayed clock in parallel to the functional flip-flops for timing error detection through duplication and comparision. This arrangement suffers from the "short path" problem, whereby the activation of paths shorter than this timing skew can cause false errors to be flagged. The traditional solution...
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