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This paper describes a systematic approach to design FPGA package for current carrying capability. As we examine silicon, interposer, and package, the profound challenge is found to meet the lifetime of high power device against the greater chance of failures owing to worsen electro-migration in every interconnect level. Our approach consists of practical methodologies to estimate current distribution...
Silicon Interposer with Through Silicon Via (TSV) is a newly developed technology that enables multichip integration and offers great potential to improve system performance with less delay, higher wiring density, and lower power consumption. One challenge of this new technology is to maintain the PDN electrical performance. Micro bumps, TSV, interposer front and back side Re-Distribution Layer (RDL)...
Power delivery net (PDN) is vital for FPGA and structural ASIC devices packages to deliver power supply with high fidelity from system board to IC chips, which requires low impedance maintained over the entire frequency range of device under operation. Many efforts have been spent to lower PDN impedance, including increased use of on-die, on-package and on-PCB decoupling capacitances. In this study...
This paper discusses the die-package-PCB co-design methodology and proposes an effective modeling technique for package-PCB co-simulation. This technique accurately takes into account the discontinuities at the package-PCB interface. The proposed new methodology renders the co-simulation 2-5X less time consuming than traditional practice. Based on the new methodology, a multi-layer multi-channel BGA...
This paper presents the dominant contributors of mutual inductance in wire-bond package thru study on the return path. The study is validated through real device measurement correlation. Based on the study, techniques to reduce crosstalk in wire-bond package will be presented which will be beneficial to the packaging world as bond wire continues to be the dominant technique to connect die to the package...
In this Paper, we propose a Quick Crosstalk Estimation Methodology by using Crosstalk Superposition Theory. An existing FPGA device package was chosen as the real test case for this study. For both microstrip and stripline, the designs were modeled by using Ansoft SI2D extractor, and the mutual matrix models extracted were used in crosstalk simulation conducted by using Agilent Advance Design System...
This paper presents the dominant contributors of mutual inductance in wirebond package thru study on the return path. The study is validated through real device measurement correlation. Based on the study, techniques to reduce crosstalk in wire-bond package will be presented which will be beneficial to the packaging world as bond wire continues to be the dominant technique to connect die to the package...
A design of the proper frequency behavior of a power distribution network (PDN) of input/output (I/O) circuitry of an FPGA enhances performance and is able to withstand synchronous switching noise (SSN) for applications in specific frequency bandwidths. A methodology of PDN evaluation and modeling is presented in this paper, with different types of packages having on-package decoupling capacitance...
This paper discusses the fundamental constraints of current packaging technology and how they affect the performance of multichannel 10-Gbps FPGAs. FPGA packages act as interconnects between dies and system boards. While IC chips take advantage of Moore's law for dimension and cost reduction, system boards traditionally have not. From design optimization practice, we conclude that the inherent dimension...
This paper discusses recent progress made in power distribution network (PDN) characterization, modeling and hardware-to-model correlation in Altera. A complete methodology and process are introduced for accurate PDN measurement and associated equivalent RLC parameter extraction. The proposed method is validated through modeling and measurement correlation and believed to be beneficial to system users...
Simultaneous switching noise (SSN) and its behavior have become increasingly important in high-performance FPGA system design featuring hundreds of I/Os transmitting in parallel at low supply voltage standard. In this paper, we present an in-depth study on SSN by analyzing its behavior in three different domains: time, frequency, and noise spectrum. Cross correlation in these three domains reveals...
Rotation is a basic operation for image processing, and the complexity of its computation is considered as the key problem of the implementation of real-time visual system. This paper proposes a novel architecture based on modified compensated CORDIC and bilinear interpolation algorithms in a recursive and folded way. The proposed modified compensated CORDIC algorithm compensates the scale factor...
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