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Modern computer systems have large amounts of DRAM running at fast cycle times. JEDEC standards for DDR3 DRAMs set the bounds of operation, but there is significant opportunity for maximizing the operating performance and reliability by optimizing the electrical parameters and the register settings across the many DIMMs in a system. Specifically, it is essential for the system designers to maximize...
A new technique for frequency-domain compliance testing of high-speed differential interfaces is implemented in a signal integrity simulation tool that can accurately predict a channel's bit-error rate (BER) from seven frequency-domain parameters. This greatly increases the speed and efficiency of designing the number of computer systems required for custom configurations in scale-out data centers...
DIMMs built with DDR4 (Double Data Rate 4th-generation) SDRAM (Synchronous Dynamic Random-Access Memory) are the current memory components used on HPC (High Performance Computing) systems. The DDR4 signal interfaces operate up to a 3200 Mbps data rate and at 1.2 V. This is a higher frequency at a lower voltage, therefore lower power, than the third generation DDR3 DIMMs. The higher frequency and lower...
Optimization of memory power is an important design objective in any computer device. However, servers are especially a challenge because the number of DRAMs are large and in aggregate can consume up to 40% of the overall system power. This paper presents power measurement experiments under a variety of server system conditions. Some techniques are proposed to optimize the overall power consumption...
This paper investigates channel/link frequency domain compliance in order to predict compatibility with a bus's chip I/O circuitry at its ends. Any channel can be associated with certain frequency domain parameter values which are easily calculated from the channel S-parameter matrix. A set of frequency domain parameters that can sufficiently describe a channel are defined in this paper. Using a genetic...
A well defined power supply tolerance specification is very important for designing processor circuits with sufficient performance margin. We introduce a design flow to derive the voltage tolerance specification by including power noise components due to the significant contributors, namely, voltage drop, voltage gradient, middle frequency chip package resonance noise, high frequency simultaneous...
Bottom Surface Metals (BSM) pin assignment for high frequency signals on a package device is a tedious manual job. Recently, [3] proposed a network flow based method to assign BSM automatically for one layer without routing blockages. In this paper, we extend the work of [3] to do BSM pin assignment on multiple layers with routing blockages. [3] also considers BSM differential pairing constraints,...
Accurate channel simulations of package interconnections require passive and causal models that faithfully represent the full frequency response from tens of gigahertz to DC. In this paper, we propose and test a method to create accurate models extending to DC while retaining passivity and causality. The model derived by this method is suitable for transient simulations of packaging interconnect systems.
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