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In this paper, an FPGA-based implementation of Frequent Items Counting is proposed. The architecture deploys the equality comparator matrix for comparing the input items with themselves to count them instantly within a single operating clock. The proposed architecture is applied to the case of the 8-bit item. That means 256 different types of items in total. The system is built and verified on the...
Recent years have witnessed a massive growth of global data due to the ubiquitous internet-of-thing products, social networking services, and mobile devices. Fast database analytics, therefore, has been increasingly attractive to numerous research. In this paper, a low-latency FPGA-based Database Processor (DBP) using bitmap index is proposed. By exploiting available embedded memory blocks and logic...
In this paper, a low-resource low-latency hybrid adaptive COordinate Rotation DIgital Computer (HA-CORDIC) is implemented both in FPGA and 180-nm CMOS technology. The adaptive algorithm reduces around 50% iterations in comparison with the conventional CORDIC algorithm. The hybrid architecture together with resource sharing, parallel and pipeline processing are utilized in HA-CORDIC implementation...
A CAM-based matching system for fast exact pattern matching is implemented on ASIC, using 65nm SOTB process, for very low power consumption. The system has a simple structure, which consists of Content Addressable Memory (CAM), AND, SHIFT, and an FSM, does not employ Central Processor Unit (CPU) as well as complicated algorithms. We take advantage of CAM which has an ability of parallel multi-match...
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