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This paper presents a sub-1V dynamic comparator with cross-coupled latches at multi-GHz operation. The low-voltage cross-coupled latches structure with a separated tail current can be used to optimize the speed and the offset in the latched stage, respectively. A high speed readout circuit is also proposed to further enhance the speed of the comparator. With BER=109, the comparator achieves 143fJ...
This paper demonstrated a 5GSample/s track and hold amplifier with 65nm CMOS process. For 6bit ADC application, this work has over 42dBc of SFDR to offer a low distorted signal. The source-degenerated source-couple amplifier with peaking inductance is employed to expand the signal swing and bandwidth, while the power dissipation is maintained as low as possible. The measured power dissipation is 48...
This paper reports on the implementation of a CMOS comparator for medical imaging applications. Design philosophy along with the conceptual imaging architecture, system requirement, associated considerations, and circuit details is discussed. Experimental results from the fabricated chip are given as proof of concept.
A high speed, low delay/log(ΔVin) dynamic comparator using negative resistance combined with input differential pair is proposed and designed in TSMC 90nm CMOS process technology. The delay/log(ΔVin) of the comparator is 22ps/dec and consumes 213μW at 3GHz clock rate and 1.2V supply. The standard deviation of the comparator input refer offset is 25mV.
In this study, we introduce a far field-aware system on a chip (SOC) design for sound source location, which is implemented with 0.18-μm CMOS process. The adopted method for the proposed system is based on average magnitude difference function (AMDF). In order to effectively detect the acoustical source in actual environment, we integrate this system with voice active detection (VAD), which can actively...
At high conversion speed, time interleaving provides a viable way of achieving analog-to-digital conversion with low power consumption, especially when combined with the successive-approximation-register (SAR) architecture that is known to scale well in CMOS technology. In this work, we showcase a digital background-equalization technique to treat the path-mismatch problem as well as individual ADC...
This paper presents a 6-bit, 1.2-GSample/s flash ADC with new proposed wideband track-and-hold amplifier (THA) fabricated in TSMC 0.13-mum CMOS technology. The wideband THA employs a front-end super source follower (SSF), which has a very low input capacitance of only 0.2-pf, to boost analog bandwidth without any on-chip passive inductor. Moreover, the flatness of the data bandwidth of ADC will improve...
This paper presents a 6-bit, 1.2-GSample/s flash ADC for MB-OFDM UWB receivers fabricated in TSMC 0.13-mum CMOS 1P8M process. Using a dedicated track-and-hold amplifier (THA) at front, it can eliminate different paths skew between comparators and clock jitter degradation to the comparators. Moreover, the proposed converter is designed with averaging and interpolation technique so that the offset of...
In this paper, the design techniques and considerations for each building block required for analog signal processing in HD-DVD PRML read channel are presented and the procedures of analog signal processing are also described. The analog front-end circuitry (AFE) includes the circuits of RF summer, attenuator, equalizer, AGC and ADC. The equalizer is constructed by seven-pole two-zero 0.05 degree...
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