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For the reliability considerations, a 60-V power p-channel LDMOS transistor co-designed with none-OD zone in the bulk end by a 0.25-μm process will be evaluated in this paper. From the experimental data found that as the none-OD zones inserting, meanwhile the none-OD zone percentage was increased, the anti-ESD capability will be strengthened too, i.e. its It2 value is improved by using this manner...
Both drain-side and source-side engineering by adding Nad and Pad layers to obtain a weak snapback characteristic nLDMOS are presented in this work. It is a novel method to reduce trigger voltage (Vt1) and to increase holding voltage (Vh). These efforts will be very suitable for the HV power management IC applications. Meanwhile, in this work, we will discuss trigger voltage and holding voltage distributions...
This work is referring to the nMOSFET singer-finger, multi-finger structures under the Electro-Static Discharge (ESD) zapping, and to evaluate the current distribution situations. By using the TCAD and HSpice, because of the internal parasitic resistance differences in each one finger, which can cause non-uniform turned on. Meanwhile, with different interior parasitic capacitor on each nMOSFET type,...
Electrical characterization of various capacitors and resistors on PEI and PET substrates is performed. The resistive inks with various nominal sheet resistances have been used. Capacitor was made using BaTiO3 dielectric layer. The screen printing process is used to manufacture the resistors and capacitors according to the recommendations of manufacture parameters. The effects of different resistor...
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