The Infona portal uses cookies, i.e. strings of text saved by a browser on the user's device. The portal can access those files and use them to remember the user's data, such as their chosen settings (screen view, interface language, etc.), or their login data. By using the Infona portal the user accepts automatic saving and using this information for portal operation purposes. More information on the subject can be found in the Privacy Policy and Terms of Service. By closing this window the user confirms that they have read the information on cookie usage, and they accept the privacy policy and the way cookies are used by the portal. You can change the cookie settings in your browser.
Design of robust power supply system to support DDR4 interface operating at 2400Mbps and beyond requires full consideration of supply noise impact on timing jitter in the system. Using relative jitter for DQ vs DQS and CA vs CK is critical and absolute jitter for CK is critical in optimizing the power supply system and deriving supply noise mitigation strategy.
The power integrity characterization of a high-capacity, compute-server memory system operating at 4.8Gbps-per-link is presented. The design robustness of the low-swing, single-ended signaling is verified as the system has excellent immunity to the noise from simultaneously switching outputs (SSO) and a low power-supply-induced jitter (PSIJ) at the primary chip-package resonance frequency.
A memory system that meets the bandwidth, power efficiency, and capacity needs of future computing systems is presented in this paper. A 6.4 Gbps single-ended DDR memory interface for the controller and the DRAM was designed in a 28-nm CMOS process for a main memory system with dual-rank DIMMs. The architecture features a novel clocking scheme, per-pin timing adjustment, dynamic point-to-point signaling...
Set the date range to filter the displayed results. You can set a starting date, ending date or both. You can enter the dates manually or choose them from the calendar.