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We present a low overhead technique that can be used to offset both large systematic and random process delay variation in the near-threshold voltage operation region. We present an analysis of this this technique applied to a 65nm CMOS self synchronous FPGA that is capable of operation from 2.0V to 0.37V. By using dual voltage supplies, we can offset gate-level pipeline stages that show large delay...
In this paper we present an autonomous watchdog circuit for error robustness which can detect logic errors caused by power supply noises and soft errors, with the smallest overheads compared to current research. The proposed watchdog circuit is realized with the dual-pipeline self synchronous system, without the need to duplicate logic. The watchdog circuit prevents error propagation through the logic...
A 65nm self synchronous field programmable gate array (SSFPGA) which uses autonomous gate-level power gating with minimal control circuitry overhead for energy minimum operation is presented. The use of self synchronous signalling allows the FPGA to operate at voltages down to 370mV without any parameter tuning. We show both 2.6× total energy reduction and 6.4× performance improvement at the same...
A 65 nm self-synchronous field programmable gate array (SSFPGA) with delay insensitive operation and pipeline granularity at the gate level, is shown to be robust to process voltage and temperature (PVT) variations. The proposed SSFPGA employs a 38 38 array of four-input, three-stage self-synchronous configurable logic blocks, with the introduction of a new dual tree-divider four-input,...
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