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MuGFET devices show good gate-to-channel control, reducing short channel effects and increased current drive [1] and their performance can be improved through implementation of mechanical stress in the silicon fin. In th is wor k we study t he stress distr ibution and transconductance behavior in unstrained and biaxially + uniaxially strained tri-gate SOI nMOSFETs with different fin dimensions through...
This paper investigates the drain read bias impact on the FB-BRAM performance of Ultra Thin Buried Oxide (UTBOX) Fully Depleted Silicon On Insulator (FDSOI) devices. Both simulations and experimental results are used. Two read regimes are clearly observed. In the read regime at higher drain voltage, impact ionization is occurring and this result in a higher sense margin and a lower retention time...
In this paper we explore, from DC measurements, the impact of gate length scaling on the main digital/analog parameters of Ultra-Thin Buried Oxide (UTBOX) Fully Depleted Silicon-on-Insulator (FDSOI) devices at different temperatures. Standard junction reference devices are compared with the extension-less ones where the latter present superior characteristics for smaller device lengths such as improved...
This paper presents an analysis of the bipolar effect in triple-gate n- and p-SOI devices with high-k/TiN metal gate. High-k dielectrics and thicker TiN achieve a larger trigger voltage. However, a reduced program window is found for MuGFETs with high-k dielectrics. p-FET devices give rise to a smaller sense margin and program window due to the reduced hole mobility. Narrow fin devices exhibit a larger...
The stress profiles extracted showed that the variation in the silicon fin dimensions influence the stress levels and distributions along the silicon fin. From the analog performance view, these variations in the stress have influence on some electric parameters. The reduction of the total fin length showed no significant change in the parameters, although a reduction in the stress level was noticed,...
In this work the proton irradiation influence on basic and analog parameters of triple-gate SOI MOSFETs is investigated. The studied devices are strained and unstrained p- and nMuGFETs. The type of stress considered in each case, was the stress that results in a better performance of p- (CESL) and n-devices (sSOI+CESL). Although the results showed the worse behavior for post-irradiated nMOS transistors,...
In this paper, the combination of the Dynamic Threshold (DT) voltage technique with a non-planar structure is experimentally studied in triple gate FinFETs. The threshold voltage, subthreshold swing, transconductance, conductance, resistance and Drain Induced Barrier Lowering (DIBL) will be analyzed in the DT mode and the standard biasing configuration. The results indicate that the DTMOS FinFET structure...
The impact of a 60 MeV proton irradiation on the drain induced barrier lowering is investigated for tri-gate FinFETs processed with and without the implementation of different biaxial or uniaxial strain engineering techniques. A contrasting behavior is observed for n- and pFinFETs, which may be associated with the radiation-induced charges in the buried oxide and the influence of the back channel...
The Zero Temperature Coefficient (ZTC) is investigated experimentally in planar and standard/biaxially strained triple-gate nFinFETs fabricated on SOI wafers. In this work a simple model to analyze the behavior of the gate-source voltage at the Zero Temperature Coefficient point (VZTC) is proposed in the linear and saturation operation regions. The analysis takes into account the temperature variations...
From the analog performance perspective, there is a fin cross-section shape influence on electric parameters. At weak inversion levels the gm/ID is shape dependent, while for moderate and strong inversions the strain type is dominant, where the mobility starts to play an important role. The output conductance and the Early voltage show a strong dependence on both fin shape and strain type. For thinner...
SOI multiple-gate devices (MuGFETs) have shown to be promising choices to continue scaling. The devices show excellent gate control and thus reduced short-channel effects. Additionally, by using high-k dielectrics a gate leakage current reduction can be achieved. The incorporation of nitrogen into these high-k materials can improve their thermal stability, reduce the dopant penetration and allow further...
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