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ALU is an integral part of the processor. And it is also one of the highest power density location in the processor. Hence in order to optimize the performance of processor, it is important to optimize the ALU. In this paper, proposed ALU having 8 functions has been designed using optimized adder structure. Also, use of pass transistors based multiplexer reduces the transistor count to around 80%...
Linearity in CMOS active inductors is a function of incoming RF input signal amplitude. As the input signal amplitude increases, inductance of the active inductor also increases, thus degrading its linearity. Nonlinearity of MOS transconductance has a significant impact on the DC operating point of active inductors. Both second-order and third-order MOS transconductance nonlinearity contributes to...
Adders are basic integral part of arithmetic circuits. The adders have been realized with two styles: fixed stage size and variable stage size. In this paper, fixed stage and variable stage carry skip adder configurations have been analyzed and then a new 16-bit high speed variable stage carry skip adder is proposed by modifying the existing structure. The proposed adder has seven stages where first...
In this work, the performance of ring counter is improved using pulsed latch technique. In high speed and low power VLSI applications where heavy pipelining is used, there is requirement of low power edge triggered flip flops. The migration from flip flop to pulsed latch has become great success in low power VLSI application. The proposed circuit has been designed using Cadence Virtuoso in 90 nm CMOS...
Last few decades have shown that the low-voltage (LV) low-power (LP) IC designs have been given a great attention as power consumption has become a great challenge. This paper demonstrates implementation of OTA and its application in low pass filter design using bulk-driven MOS transistors (MOST), bulk-driven dynamic threshold MOST, bulk-driven floating-gate MOST and bulk-driven quasi-floating-gate...
A new interface circuit for readout of HgCdTe Infrared photodiodes is proposed that can be used for efficient transfer of photocurrent from the photodiodes to the integration capacitor of the readout integrated circuit (ROIC). This ultimately results in high sensitivity and improved IR images. A high gain amplifier in the feedback path between gate and drain of the input transistor of standard gate...
The technique of body biasing has achieved great success in modern IC design as in it, is possible to alter the threshold voltage of MOS transistor so that device leakage and timing performance can be improved. In this paper a Schmitt trigger circuit has been designed using four types of body bias techniques. The proposed circuits were simulated in SPICE 180nm CMOS technology parameters. A comparative...
In this paper we report a low voltage differential amplifier based on self-cascode topology which is suitable for low voltage and high speed operation. A negative conductance is used that will cancel the positive output conductance of an amplifier. As a result the total equivalent output conductance is reduced and thereby the overall voltage gain of the amplifier is increased. Using this technique...
Today power dissipation is the most critical problem in Low Power circuits in VLSI design. Adiabatic technique is a technique to reduce power dissipation in digital circuits in which energy stored in a capacitor can be recycled rather than dissipated as heat. In this paper the Fat tree decoder incorporating PFAL i.e. Positive Feedback Adiabatic Logic technique has been simulated using SPICE simulation...
In this paper, a low voltage Schmitt trigger has been designed using various low voltage MOS transistor implementation techniques namely-Dynamic Threshold MOS (DTMOS), Multiple threshold MOS (MTMOS), Variable threshold MOS (VTMOS) and Floating gate MOS (FGMOS). The conventional and proposed circuits are designed in 180nm CMOS technology from TSMC and simulated at 0.5 Volts. The comparative study of...
This paper shows an effective and novel implementation of the self-cascode technique in the design of a CMOS active inductor in 65nm CMOS bulk technology with a triple-well process. The current operated active inductor operates at a self-resonant frequency of 0.447 GHz at a relatively low bias current (less than 150 uA) drawn from a 1.2 V voltage supply. The design methodology of the self-cascode...
In this paper, we have proposed a new low voltage, highly accurate Flipped Voltage Follower Self Cascode (FVFSC) current mirror which has a high input linear range and also possess high current copy accuracy. Input linear range of the proposed FVFSC current mirror has been increased to 980 μA i.e., enhanced by a factor of 2. The proposed and conventional circuits have been designed at 180nm technology...
Low power circuit techniques have become indispensable need of the hour for VLSI design. One such low power technique which has gained popularity over the past decade is adiabatic technique. It is based on the concept of reusability of power. In this paper, apositive feedback adiabatic logic (PFAL) based mux decoder is proposed. The decoder has been designed in 180nm CMOS technology and simulated...
In this paper we present the design of an ultra low power analog four quadrant multiplier based on second generation current conveyor(CCII). The main attractive feature of the proposed multiplier is that it is based on dynamic threshold MOS transistor (DTMOS). Due to use of DTMOS, the power consumption of proposed multiplier has been reduced by 99.92 percentage as compared to its conventional version...
In this work we have demonstrated a novel technique to achieve high bandwidth in differential amplifier. This technique is based on using a composite transistor configuration consisting of dynamic threshold MOS transistor (DTMOS) and a source follower. This composite transistor has higher value of transconductance and bandwidth than conventional DTMOS. The use of this technique increases the bandwidth...
In this work a current regulated CMOS active inductor is proposed using dynamic threshold MOS transistor (DTMOS). The proposed active inductor is based on the gyrator-C approach with positive transconductance stage realized by DTMOS. The bandwidth and linearity of proposed inductor is improved using a new approach. The proposed approach is based on simultaneous use of inductive peaking and feed-forward...
This paper presents a new approach for increasing the gain of CMOS Class-E amplifier. The proposed approach is based on using dynamic threshold MOS transistor. The proposed amplifier is able to work at a low supply voltage of 1V and consumes a very small power. The proposed class-E amplifier offers very stable sinusoidal signal to drive the load. The most attractive feature of the proposed amplifier...
In this paper, we have proposed a new approach to improve the bandwidth of unity gain voltage follower. This approach is based on using a dynamic threshold MOS transistor (DTMOS). The bandwidth of the proposed voltage follower has been enhanced by a factor of nearly 2.5. Use of DTMOS transistor also improves the input signal range of the proposed voltage follower. The proposed and conventional circuits...
This paper presents an attractive approach for bandwidth extension of a four quadrant CMOS analog multiplier. The proposed approach is based on using dynamic threshold MOS transistor (DTMOS) which is an effective technique that achieves supply voltage reduction with a simultaneous increase in the overall transconductance of the MOS transistor. The proposed multiplier can operate at very high frequencies...
In the past body terminal was considered as an exclusive source of unwanted second order effects. But recently use of body terminal is becoming an attractive opportunity for improving the performance of analog integrated circuits. Low frequency harmonic distortion stems from the body effect and is dependent on body effect coefficient. In most of the analysis, body effect present in conventional flipped...
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