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Accurate peak power measurement requires detailed switching and delay information for each signal over the entire simulation. Performing a full signal dump and power calculation for a long simulation run usually spends a large amount of time and disk space. In this paper, we propose an Essential-signal-based methodology which only performs power analysis over a small subset of the original simulation...
Nowadays Graphic Processing Units (GPU) are gaining increasing popularity in high performance computing (HPC). While modern GPUs can offer much more computational power than CPUs, they also consume much more power. Energy efficiency is one of the most important factors that will affect a broader adoption of GPUs in HPC. In this paper, we systematically characterize the power and energy efficiency...
This paper reports a 0.5V SOI CMOS dynamic-threshold MOS (DTMOS)/ dual-threshold (MTCMOS) circuit technique for design optimization of low-power SOC applications. Via the DTMOS/non-DTMOS technique for implementing the SOI version of the gate-level dual-threshold static power optimization methodology (GDSPOM), a 16-bit multiplier circuit has been designed, showing a performance with 30% less power...
Bipolar resistive switching memory device with a low power operation (200 muA/1.3 V) in a W/Ge0.4Se0.6/Cu/Al structure has been investigated. A stronger Cu chain formation can be observed by monitoring both the erase voltage and current. The low resistance state (RLow) decreases with increasing the programming current from InA to 500 muA, which can be useful for multi-level of data storage. This resistive...
A low-power single-chip Bluetooth EDR device is realized using a configurable transformer-based RF front-end, a low-IF receiver and direct-conversion transmitter architecture. It is implemented in a 0.13mum CMOS process and occupies 11.8mm2. Sensitivity for 1, 2 and 3Mb/s rates is -88, -90, and -84dBm and transmitter differential EVM is 5.5% rms.
This paper presents a 65nm low power technology offering a dual gate oxide process, multiple Vt devices at a nominal operating voltage of 1.2V, a nine level hierarchical Cu interconnect back-end of line process with low k dielectrics and 0.676mum2 and 0.54mum 2 SRAM cells, optimized for performance and density, respectively. The key focus of this technology has been low cost, process simplicity and...
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