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This paper presents the methods of eliminating the plasma-induced Si substrate damage in periphery regions, resulting from high aspect ratio etching process for 3D NAND fabrication. The impact of Si substrate damage is verified by the low and high bias power experiments. The result indicates more Si damage is present with high energy bombardment; therefore, high bias power is recommended to be inhibited...
We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.
We present several efforts for arcing reduction during high aspect ratio etching. Strategies including pulsing etching adjustments, ex situ multi-cyclic etch approach, flush step incorporation, E-chuck voltage operation, cap material, etc. are explored. The details are discussed in the paper.
A novel three-dimensional (3D) NAND structure containing both vertical gate (VG) framework and gate-all-around (GAA) cell structure is innovated and demonstrated. It is fabricated on alternating layers of silicon dioxide (OX) and polysilicon (PL) by using 43nm technology. To our knowledge, one of the major advantages of the novel structure is the smaller cell unit footprint than vertical channel (VC)...
Pattern dependent charging effect is explored in this study. Due to increased film thickness in 3D NAND structure, a derivative problem-the plasma-induced charging damage is enhanced during high aspect ratio (HAR) etching. In this paper, several effective methods are demonstrated to alleviate the impact of profile distortion due to charging effect while etching high aspect ratio (>14) trenches.
NF3/NH3 remote plasmas are used in oxide etch back process prior to the salicide process of word lines (WL) owing to high etch selectivity of silicon oxide over polysilicon. The etch saturation behavior which performs etch stop with a certain period of process time is one of the interesting characteristics during oxide etch process by employing NF3/NH3 remote plasmas. In this study, it is found that...
Down-flow plasma etching is mentioned instead of high-density capacitively coupled plasma (CCP) etching to prevent the control gate (CG) against physical damage during the intra-level dielectric (ILD) etch back, which is the process prior to form cobalt silicide word lines. However, owning to lack of ion bombardment, it is hard to achieve good etch uniformity. This paper presents the design of experiments...
Severe and unexpected yield loss (∼26% in avg.) is found in the early development stage of the advanced flash memory. The major failure mode, array bridging contact, is revealed as the root cause and mainly induced by undercutting photo-resist (PR) profile. In this work, a novel scheme, anti-etch bottom anti-reflective coating (anti-etch BARC), is used instead of the conventional dual ARC (BARC/dielectric...
The authors investigated the correlation between variation of post-etch critical dimension (ECD) and etcher chamber condition during floating gate etching process. This paper presents the significantly effective method of utilizing the SF6/O2-based very long plasma-chamber cleaning or the novel Transformer coupled plasma (TCP) window temperature design not only achieves a stable gate CD (CD variation...
This paper identifies post etch killer defects, e.g., core bridging, small particle and tiny bridging, and investigates the possible solutions in a SADP module. Among the killer defect adders, core bridging and small particle are commonly observed after the oxide core removal by BOE. Core bridging adder is a carbon-containing polymeric by-product during nitride spacer open; by introducing additional...
This paper describes the advanced control technology of critical dimension uniformity (CDU) by flash gate stack etch process. We have investigated the effective way of utilizing Tri-layer approach, which not only reduces the influence of topology step-height but also improves the range of ECD within die from 17.6nm to 4.9nm. Moreover, the influence of Etcher design on ECD variation becomes larger...
This paper presents a unique gate structure for reducing shorts between word lines on charge-trapping flash cell memory. In the early stage of developing sub-45 nm half-pitch word line by a self-aligned double patterning (SADP) technology, the cell array suffered from abnormal intrinsic word line-to-word line shorts, ca. 96.3% of the bridge rate on the 72 Mb cell memory, due to the formation of polysilicon...
The selected etching in lithium niobate (LiNbO 3 ) crystals is carried out by two different ion implantation and differential wet etching. The LiNbO 3 samples are cleaned and partially masked with photoresist in lithographic procedure firstly, followed by 1.5 MeV O + or Si + ion implantation at a dose of 1×10 15 ions/cm 2 at room temperature. It is found...
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