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Percolating and neck-based thermal underfills with significant improvements in thermal conductivity compared with capillary underfills are currently under development. They could be applied between dies to improve the heat dissipation through a 3D chip stack. In this parametric study, we provide insights into the thermal, mechanical, thermo-mechanical and electrical properties achievable by this new...
This paper presents wideband circuit level compact models of through-silicon via (TSV) multi-signal connections within an array. The models were developed for time and frequency domain characterization of periodic TSV array patterns, including crosstalk evaluation. A frequency dependent silicon substrate induced dispersion and loss effects are considered, as well as the skin and proximity effects...
Electrical loss and substrate noise coupling induced by through-silicon-vias (TSVs) in silicon-on-insulator (SOI) substrates is characterized in frequency and time domains. A three-dimensional (3-D) test site in 45-nm CMOS SOI including copper-filled TSVs and microbumps ('s) is fabricated and measured to extract the interconnect loss. Good correlation to the electrical circuit models is...
The paper examines the question of when and how can an on-chip transmission line have a stand-alone, independent model in the actual VLSI design environment. The study addresses a certain set of simple structures, covering most of practical VLSI design needs, which includes coplanar single and coupled structures. Based on theoretical analysis and numerical results, practical criteria of "sufficiently...
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