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This communication deals with frequency behavior of orthogonal interconnect layers on inductance in high-speed VLSI circuits. The RLC parameters of the distributed model are determined by electromagnetic simulations. We evidence the error made on inductance in the range 1-50 GHz for three traditional interconnect configurations. A time-domain analysis highlights the impact of the inductance error...
An electrical modelisation of eight lossy Cu interconnects is proposed thanks to the implementation of a vector finite element method. This full wave analysis gives frequency dependence of proper or mutual inductance, capacitance or resistance from resulting transmission line equations system. Spice results are then proposed for different set of spacing and low dielectric material in case of interconnects...
A simple design criterion is presented for obtaining maximal data rate in network on chip (NoC) links. It is shown that the maximal data rate is achieved near the boundary between RC and RLC model validity domains. The criterion is applicable to various on-chip transmission line structures, including crossing lines at adjacent metal layers. Inductive effects are represented by time-of-flight through...
The paper deals with an efficient technique to introduce non homogeneous dielectrics in a full-wave integral formulation of Maxwell's equations. The approach is based on the evaluation of the Green's functions via simulated image method. This allowed the extension of both the surface integral formulation and its numerical implementation SURFCODE to the analysis of single-layered planar interconnects...
Constant evolution in integrated circuits technology has led to an increase of the switching speed of the digital chip. As a result, there is a growing interest in the inductance associated with signal lines. Inductive coupling effects on interconnects is an emerging concern in high performance digital integrated circuits. Since global wires run on less dense upper metal layers increase wires separation...
In most applications the method of moments (MoM) generates full reaction matrices. However, in this paper, we demonstrate that sparse reaction matrices are produced when modeling stripline interconnects. This is demonstrated by investigating the sparse nature of the MoM reaction matrices that are produced when using the full-wave layered interconnect simulator (UA-FWLIS) with a parallel-plate Green's...
Increased frequencies and reduced rise times have made signal integrity simulations an integral part of high speed board designs. Signal integrity simulations are usually performed considering an ideal power source and power integrity simulations are performed assuming ideal transmission lines. But due to ever decreasing rise times errors creep into signal quality and timing analysis by ignoring the...
The impact of parasitic effects in current integrated circuits is important. One reason for this fact is the increasing operating frequency in current circuits. The router PARSY (parasitic symmetric router) is developed for routing sensitive nets. Its goal is the even distribution of parasitic effects on nets within a net pair or net group. The even distribution of the resistance is made by using...
This paper proposes a loss optimization method for a high-speed transmission line on Si LSI. One of the most important issues for a transmission line interconnection is loss reduction of signal lines. Characteristics of differential transmission lines are evaluated by on-wafer measurement. It is shown that attenuation characteristics depend on the product of a line width and a line-to-line distance...
Circuit modeling of high-frequency devices described by tabulated multi-port parameters has generated immense interest during the recent years. In most cases, simple equivalent circuit models (S-ECM) are available to the designers, which correlate well with the measured parameters at certain frequencies, however, deviate at others. Traditional efforts to improve equivalent circuit models are device-specific,...
In this paper, a passive multi-level model reduction method is presented, which is suitable for networks with large number of ports. By using prior information about the type of the loads that can be connected to the network, the congruence transformation matrix is chosen such that it minimizes the impact of the additional ports. Furthermore, an SVD based second level of reduction is utilized in order...
This paper describes a new algorithm to obtain reduced-order models for large networks with delay elements. The proposed algorithm can be used in situations where delay extraction based modeling approaches have been used to model portions of interconnects with low losses, while other portions are modeled with large networks of lumped components. It is shown that the reduced-order model is passive...
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