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A charge redistribution successive-approximation-register analog-to-digital converter (ADC) with nonbinary redundant search tree is presented. The combination of thermometer-coded and series-split binary-weighted capacitive digital to analog converters is area efficient and enables high resolution in a standard digital process without high matching requirements. A power and timing-effective latch-based...
This paper presents an analysis of capacitor mismatch of a partially thermometer coded charge redistribution SAR ADC. Thermometer coding of only the most significant bits effectively improves the linearity of a binary weighted capacitor array without exponential growth of decoder and interconnection effort at high resolutions. Distribution based calculations and an implementation example demonstrate...
This paper presents a charge redistribution successive approximation A/D-Converter with 14 bit resolution designed in a 0.35 µm CMOS technology. An enhanced self-calibration technique is applied to correct mismatch of the binary weighted capacitors of a fully differential ADC. In contrast to previous presented solutions, no additional digital calculation is permanently necessary during conversion...
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