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The combination of software flexibility and hardware configurability makes partially reconfigurable application-specific instruction-set processor (rASIP) an attractive architecture, which matches the needs of computation-intensive and fast-evolving wireless receiver algorithms. This paper describes the design of a multimode multiple-input–multiple-output (MIMO) detector by using rASIP, which supports...
The use of Multiprocessor Systems on Chip (MPSoCs) is a common practice in the design of state-of-the-art embedded devices, as MPSoCs provide a good trade-off between performance, energy and cost. However, programming MPSoCs is a challenging task, which currently involves multiple manual steps. Although, several research efforts have addressed this challenge, there is not yet a widely accepted solution...
Many embedded applications such as multimedia, signal processing and wireless communications present a streaming processing behavior. In order to take full advantage of modern multi-and many-core embedded platforms, these applications have to be parallelized by describing them in a given parallel Model of Computation (MoC). One of the most prominent MoCs is Kahn Process Network (KPN) as it allows...
Underutilization as well as oversubscription of processing resources are common problems in current accelerator-based computing systems. Facing these challenges will require intelligent algorithms for scheduling parallel workloads on accelerators. The general aim of this paper is to achieve fair distribution of the tremendous computation power of modern devices among running applications towards enhancing...
In the last years the presence of embedded devices in everyday life has grown exponentially. The market of these devices imposes conflicting requirements such as cost, performance and energy. The use of Multiprocessor Systems on Chip (MPSoCs) is a widely accepted solution to provide a trade-off between these demands. However, programming MPSoCs is still a cumbersome task. Several research efforts...
Processor models for electronic system level (ESL) simulations are usually provided by their vendors as binary object code. Those binaries appear as black boxes, which do not allow to observe their internals. This prevents the application of most existing ESL power estimation methodologies. To remedy this situation, this work presents an estimation methodology for the case of black box models. The...
Engineers of next generation embedded systems heavily rely on virtual platforms as central tools in their design process. Yet, the ever increasing HW/SW complexity degrades the simulation performance of those platforms and threatens their viability as design tools. With multi-core workstations today being widely available, the transition towards parallel simulation technologies seems obvious. Recently...
Virtual Platforms (VPs) are advantageous to develop and debug complex software for multi- and many-processor systems-on-chip (MPSoCs). VPs provide unrivalled controllability and visibility of the target, which can be exploited to examine bugs that cannot be reproduced easily in real hardware. However, VPs as used for debugging provide only traditional interfaces, such as step-based debuggers and traces,...
This paper investigates the possibility of creating an energy profile of a RISC processor instruction set in the prototyping phase, using FPGA implementation and physical measurements. In order to determine the power consumption at instruction-level, several programs have been developed and run on the processor implementation on FPGA. The experiments have focused at the following groups of instructions:...
The problem of finding an optimal allocation of logical data buffers to memory has emerged as a new research challenge due to the increased complexity of applications and new emerging Dynamic RAM (DRAM) interface technologies. This new opportunity of a large off-chip memory accessible by an ample bandwidth allows to reduce the on-chip Static RAM (SRAM) significantly and save production cost of future...
This paper presents different views exposed in a special session on the current standing of programming and design tools for multi and manycores in the embedded domain. After approximately ten years of the advent of multicore architectures, we take a look at state-of-the-art and trends in model-based programming methodologies from an academic point of view. This view is contrasted with early experiences...
Modern multi- and many-core systems are prone to concurrency-related bugs that surface only at system level. Detecting these bugs might require dealing with low-level hardware (HW) protocols and/or software (SW) inter-task interactions. Virtual platforms (VPs) offer a vehicle to conveniently debug HW/SW functionality, yet developers are mostly limited to manually breakpoint, step and interact with...
Modern cars require powerful multi- and manycore hardware platforms to fulfill the demands of upcoming computationally intensive advanced driver assistance systems. This leads to a distributed hardware/software architecture that poses an unbearable system complexity to designers. Additionally, the strict requirements of new functional safety standards make it extremely difficult to rapidly and comprehensively...
In the past memory allocation and communication between processors and memories in current MPSoC's, due to the small design space, was not a big challenge. Through advanced MPSoC's and improving techniques to interface Dynamic RAM (DRAM), allocation of logical data buffers to physical memories is no longer manageable manually. We present a heuristic for the mapping of logical data buffers to physical...
Little consideration has so far been dedicated to the investigation of the implementation complexity of stochastic detectors for multi-antenna (MIMO) systems although they promise communications performance close to max-log detection for certain SNR regimes. In this work, we propose a complete redesign of the only reported parallel VLSI architecture for soft-input soft-output Markov chain Monte Carlo...
Complexity of modern applications, the performance requirements and the power constraints are the major driving forces that motivate the use of Multiprocessor Systems on Chip (MPSoCs). Programming these platforms is still a big challenge, posing a multitude of software design issues: What is the right MPSoC programming model to capture parallelism?, How to parallelize legacy C code?, How to achieve...
EURETILE investigates foundational innovations in the design of massively parallel tiled computing systems by introducing a novel parallel programming paradigm and a multi-tile hardware architecture. Each tile includes multiple general-purpose processors, specialized accelerators, and a fault-tolerant distributed network processor, which connects the tile to the inter-tile communication network. This...
This paper introduces a novel class of linear soft-input soft-output detectors with boosted communications performance. The detector showed an SNR gain of up to 2.4 dB compared to state-of-the-art linear detectors. We introduce a low-complexity algorithm tailored for VLSI implementation, and propose a suitable architecture. The developed ASIC demonstrates the feasibility and efficiency of the concept,...
Application Specific Instruction Set Processors (ASIPs) seek for an optimal performance/area/energy trade-off for a given algorithm. In all current design methodologies an architectural model must be first manually created based on designers experience. These models are increasingly refined until the design constraints are met, through several time consuming algorithmic/architecture co-exploration...
A computational complexity analysis of matrix inversion used in soft-input soft-output minimum mean square error (MMSE) MIMO detectors and a comprehensive literature comparison of corresponding VLSI implementations are presented. They indicate that the application specific integrated circuit (ASIC) proposed in this paper is — to the best of our knowledge — the most area-throughput efficient VLSI architecture...
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