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In this paper we present a flexible circuit that allows for a parallel and partially asynchronous multiplication of matrices. The circuit, realized in the CMOS technology, has been designed for the application, for example, in fast Kalman filtering in automotive active safety applications. In such filters we encounter numerous operations performed on matrices that are time consuming. Additionally,...
This paper presents the way of implementation of fuzzy set operators at the transistor level. We propose a novel realization of basic fuzzy logic (FL) functions, such as bounded sum, bounded difference, bounded product, bounded complement, fuzzy logic union (MAX) and fuzzy logic intersection (MIN). The proposed structures of the operators may be easily connected in chains, creating larger FL systems.
The paper presents a novel circuit for the calculation of Manhattan distance between two vectors of signals, suitable for various machine learning algorithms realized at the transistor level. In Self-Organizing Artificial Neural Networks, for example, one of the basic operations is the calculation of a distance between input learning patterns and vectors of neuron weights. In pattern recognition two...
In this paper, we present a concept of a transistor level implementation of the Particle Swarm Optimization (PSO) algorithm that belongs to the group of unsupervised learning algorithms aimed at the design of artificial neural networks (ANNs). The algorithm exhibits an ability to search for an optimal solution in a multidimensional data space, in which many sub-optimal solutions may exist. The ANN...
The paper presents a novel transistor level implementation of a triangular neighborhood function (TNF) suitable for self-organizing maps (SOMs) realized as Application-Specific Integrated Circuit (ASIC). Our previous investigations have shown that using the TNF instead of more complex Gaussian neighborhood function (GNF) is sufficient to achieve good learning properties. It can be said that the TNF...
In this paper we present a 10-phases programmable clock generator for the application in control of Successive Approximation Register (SAR) Analog-to-Digital Converters (ADC), realized in the CMOS 130 nm technology. The circuit provides 10 clock signals on separate terminals (sections). The programmable feature means that we can program the number of clock phases which are cyclically repeated. The...
The paper presents a new, mixed analog-digital, circuit for analog sorting signals. In comparison to other circuits of this type the proposed solution offers large versatility. The main objective is its application in Neural Gas (NG) learning algorithm used to train unsupervised neural networks (NNs). However, the circuit can also be used in nonlinear processing of analog signals. It is capable of...
The paper presents a simple current-mode conscience mechanism used in hardware implemented Winner Takes All neural networks to eliminate the problem of the, so called, dead neurons. These neurons reduce the number of data classes that can be distinguished by the NN, i.e. they decrease the efficiency of the NN. The circuit has been realized in the TSMC CMOS 0.18 μm process. At data rate of about 10...
A novel, binary-tree, asynchronous, nonlinear Min/Max filter is presented in the paper. In the proposed circuit an input signal (current in this case) is first sampled in the circular delay line, controlled by a multiphase clock (8 phases in this case). In the next stage particular samples are converted to 1-bit signals with delays proportional to the values of these samples. In the following step...
In this paper we present the project and realization of a two-wheel, easy-to-use, Segway - type mobile vehicle. Battery powered, two-wheeled vehicles are of great and growing interest all the time. Unfortunately, solutions found on the market are still very expensive. It was the motivation behind designing own solution of this type. Presented vehicle has been designed from ground up. It is controlled...
The paper presents an optimized algorithm for the recognition of complex and noisy patterns. The system, based on the backpropagation neural network (NN), can be used in numerous applications. One of them is pattern recognition in biomedical signals, used for example in wireless body area networks. In the paper the efficiency of the system has been verified with data set composed of letters with not...
The paper presents a low power and low chip area decimation filter for a 15-bits Σ-Δ analog-to-digital converter (ADC) designed for a flywheel MEMS gyroscope. In contrary to typical solutions, in which decimation is performed after each filtering stage, in the proposed approach all filter sections operate at the sampling frequency of the modulator. The low power dissipation is in this case achieved...
The paper presents a new CMOS implementation of the initialization mechanism for Kohonen self-organizing neural networks. A proper selection of initial values of the weights of the neurons exhibits a significant impact on the quality of the learning process. A straightforward realization of the initialization block in software is simple, but in hardware it requires providing the programming signal...
The paper presents a new, precise, 16-channel measuring system for testing low energy, analog ASICs (Application Specific Integrated Circuits). The proposed system allows simultaneous testing of circuits working both in the voltage mode (in the range from −4V to 4V) and the current mode (from 1 nA to 20 mA) with resolution up to 20 bits, with a maximum frequency of one channel up to 2 kHz. Each of...
A flexible, fully programmable Winner Takes All (WTA) Neural Network (NN) has been realized on two microcontrollers (μC) with the AVR and the ARM cores placed on a single board. The proposed device is equipped with an external analog-to-digital (ADC) and four digital-to-analog (DAC) converters, which enable operation with analog signals in parallel in the real time. One of the objectives of the proposed...
The paper presents an influence of leakage effect observed in capacitive analog memories on learning process in hardware implemented Kohonen neural networks with MOS transistors used as switches connected with information holding capacitors. The learning results, i.e. variations (adaptations) of weight values, strongly depend on the transistor leakage currents. This is a cause for some quantization...
A novel current-mode, binary-tree WTA / LTA circuit for application in analog Kohonen neural networks has been presented. In the proposed circuit input currents are first converted to step signals with equal amplitudes and different delays that are proportional to the values of these currents. In the second step these delays are compared using a set of time domain comparators in the binary tree structure...
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