Serwis Infona wykorzystuje pliki cookies (ciasteczka). Są to wartości tekstowe, zapamiętywane przez przeglądarkę na urządzeniu użytkownika. Nasz serwis ma dostęp do tych wartości oraz wykorzystuje je do zapamiętania danych dotyczących użytkownika, takich jak np. ustawienia (typu widok ekranu, wybór języka interfejsu), zapamiętanie zalogowania. Korzystanie z serwisu Infona oznacza zgodę na zapis informacji i ich wykorzystanie dla celów korzytania z serwisu. Więcej informacji można znaleźć w Polityce prywatności oraz Regulaminie serwisu. Zamknięcie tego okienka potwierdza zapoznanie się z informacją o plikach cookies, akceptację polityki prywatności i regulaminu oraz sposobu wykorzystywania plików cookies w serwisie. Możesz zmienić ustawienia obsługi cookies w swojej przeglądarce.
Support Vector Machine (SVM) is a linear binary classifier that requires a kernel function to handle non-linear problems. Most previous SVM implementations for embedded systems in literature were built targeting a certain application; where analyses were done through comparison with software implementations only. The impact of different application datasets towards SVM hardware performance were not...
Multiprocessor embedded systems integrates diverse dedicated processing units to handle high performance applications such as in multimedia and network processing. However, lock-based synchronization limits the efficiency of such heterogeneous concurrent systems. Hardware Transactional Memory (HTM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, HTM...
Hardware Transactional memory (HTM) performance is application-specific and is dependent on its version management and conflict management configurations. An adaptive mechanism is needed to adapt its configurations based on multiple application behaviour.
This paper presents a remote dynamically reconfigurable platform using NetFPGA development board. The functionalities of execution units in this platform can be updated remotely through the 1Gbps Ethernet connection without assistance from the NetFPGA host computer. This is achieved by designing custom reconfiguration controller and utilizing the Internal Configuration Access Port (ICAP) available...
Transactional memory (TM) is a promising approach in creating an abstraction layer for multi-threaded programming. However, the performance of TM is application-specific. Previous embedded system TM implementations exploit only conflict management to suit the application requirements. In this paper, we propose a hardware transactional memory (HTM) which exploits both version and conflict management...
Buffer insertion is a very effective technique to reduce propagation delay in deep sub-micron VLSI interconnects. As design dimension shrinks, more buffers are needed to improve timing performance. However, the buffer itself consumes power and it has been shown that power dissipation overhead due to buffer insertions is significantly high. Many methodologies to optimize propagation delay with power...
Performance optimization in very-large-scale integration (VLSI) design is the key success in today's design automation methodologies. One of the performance issues is the interconnect delay in deep sub-micron VLSI circuits. The interconnect delay becomes more dominant compared to gate delay when the size of the gates is reduced. This paper presents an algorithm to optimize the timing performance of...
Network-on-chip (NoC) has been introduced as a promising on-chip communication architecture to support many IP (intellectual property) cores on a single chip. Application mapping of IP cores onto a NoC topology is considered as a NP-hard problem. The increasing number of IP cores makes NoC application mapping more challenging to obtain optimum core-to-topology mapping. This paper proposes a genetic...
Buffer insertion and wire sizing have been proven effective in solving the timing optimization problem in VLSI interconnect design. In this paper, we describe a graph-based maze interconnect routing algorithm for VLSI designs. An interconnect routing and buffer insertion with look-ahead algorithm is used to construct a maze routing path. Simultaneous routing with buffer insertion and wire sizing is...
Manipulation of wire sizing, buffer sizing, and buffer insertion are a few techniques that can be used to improve time delay in very large scale integration (VLSI) circuit routing. This paper enhances an existing approach, which is based on Particle Swarm Optimization (PSO) for solving routing problem in VLSI circuits. A two-step Binary Particle Swarm Optimization (BPSO) approach, which is based on...
The performance of very large scale integration (VLSI) circuits is depends on the interconnected routing in the circuits. In VLSI routing, wire sizing, buffer sizing, and buffer insertion are techniques to improve power dissipation, area usage, noise, crosstalk, and time delay. Without considering buffer insertion, the shortest path in routing is assumed having the minimum delay and better performance...
Buffer insertion and wire-sizing in very large scale integrated circuit interconnect routing are multi-constraint optimization problem, optimizing constraints such as delay, skew, area, and power. This paper proposes a multi-constraint VLSI interconnect routing technique, called MCRouting, that optimizes different constraints such as delay and buffer area through simultaneous wire-sizing and buffer...
The design of VLSI circuits today has become very challenging indeed. The main factor affecting system performance is the interconnect delay. Many algorithms have been proposed to solve the interconnect timing optimization problem. Research has shown that techniques like buffer insertion and wire-sizing have been proven to be very effective in reducing interconnect delay. This paper describes a graph-based...
Podaj zakres dat dla filtrowania wyświetlonych wyników. Możesz podać datę początkową, końcową lub obie daty. Daty możesz wpisać ręcznie lub wybrać za pomocą kalendarza.