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Super-resolution technologies are used to fill the gap between high-resolution displays and lower-resolution contents. There are various algorithms to interpolate information, one of which is using a convolutional neural network (CNN). This paper shows FPGA implementation and performance evaluation of a CNN-based super-resolution system, which can process moving images in real time. We apply horizontal...
This paper proposes an FPGA implementation of a simple and reliable method for real-time peak detection of time series data. Focusing on an existing off-line method called Automatic Multiscale Based Peak Detection (AMPD), we show, how the original AMPD algorithm is modified to be an on-line method and how it is applied on an FPGA. To validate the accuracy of our design, simulation results in a case...
This paper deals with the real-time FPGA implementation of the posterior system state estimation in dynamic state-space models using a particle filter. The system is constructed by parallel resampling (FO-resampling) algorithm on a stream-based architecture. In particular, the system consists of three steps: prediction, likelihood calculation and resampling. Since the resampling is accomplished in...
In order to apply the CPU to the control system for the renewable energy plant which is usually installed in the isolated place, there are a lot of issues e.g. the cooling, the power conservation and the parts exchange with the device life cycle. The undetectable dangerous error of the control system is also a big issue for such the isolated plant with the long term operation, because it causes the...
For the renewable energy system, the power conservation and the low heat emission of the control system are big issue. Since those energy plants are installed in the natural environment which is inconvenient for the maintenance, it is very important that the control systems are supplied and maintained for long term without any development risk. The performance of the current CPU depends on the number...
The purpose of this paper is to present the digital overcurrent detector for the peak current mode dc-dc converter which has been already applied to the server for the data center. The proposed peak current detection circuit is composed of the RC integrator and comparator as the A-D converter for the detected current. The proposed method can detect the overcurrent by using the RC integration time...
The data center of the cloud which supports the recent communications infrastructure requires the high reliable control systems in order to control its enormous electric power and exhaust heat. It is important to reduce the energy wasted by the control systems. The FPGA is watched because of the low energy, the long sustainability, and the simple architecture. It is clarified that the FPGA realizes...
This paper proposes an FPGA-based soft core processor architecture equipped with a configurable accelerator to speed up GF(2m) arithmetic for elliptic curve cryptography (ECC) systems. Focusing on the fact the number of operations required for GF(2m) arithmetic is influenced by the relationship between the irreducible polynomial and the machine word size, we propose an approach where the word size...
This paper presents implementation and evaluation of an accelerator architecture for soft-cores to speed up reduction process for the arithmetic on GF(2m) used in Elliptic Curve Cryptography (ECC) systems. In this architecture, the word size of the accelerator can be customized when the architecture is configured on an FPGA. Focusing on the fact that the number of the reduction processing operations...
In this paper, we discuss user space parameters and performance modeling of 3-D stencil computing on a stream-based FPGA accelerator. We use a heat conduction simulation as a benchmark and evaluate a performance for that developed with MaxCompiler, a kind of high-level synthesis tools for FPGAs, and MaxGenFD, a domain specific framework on the MaxCompiler for finite-difference equations. Performance...
This paper presents a fast response digitally controlled full bridge converter in parallel operation. The digital controlled circuit has some problem. One of the main problems is the delay time. The delay time includes the conversion time of A-D converter and processing time of digital controller. It exerts a bad influence on the dynamic characteristic. In the proposed method, the sample timing for...
The purpose of this paper is to present a digitally controlled dc-dc converter with a novel peak current injected technique. In the proposed method, the peak current is able to be detected by using a voltage controlled oscillator (VCO) which is very low cost and the simple delay circuit implemented by the a field programmable gate array (FPGA). As a result, it is confirmed the main switch is turned...
This paper presents a new digital peak current mode dc-dc converter using a FPGA delay circuit and a simple A-D converter. The peak current detection circuit is only composed of RC integrator and field programmable gate array (FPGA) delay circuit. The sampling point of detected current is changed by the feedback value of output voltage. The RC integrator is performed as the A-D converter for the current...
In this paper, deep pipelined FPGA implementation of a real-time image-based human detection algorithm is presented. By using binary patterned HOG features, AdaBoost classifiers generated by offline training, and some approximation arithmetic strategies, our architecture can be efficiently fitted on a low-end FPGA without any external memory modules. Empirical evaluation reveals that our system achieves...
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