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Introduction: The trend towards digitization of healthcare promises a future of improved, insight driven, more economical and patient-centered care models. Besides digitization of health records, it has spurred massive research in nano- and bioMEMS devices that sense health related parameters in a compact format. A myriad of devices including innovative CMOS FET structures, nanophotonic and nanomechanical...
In this paper we will report on full wafer electrical characterization based on resistance of various lengths of daisy chain ranging from 10 to 100 TSV's. The resistance of single TSV including metal contact is in range from 5~20 mOhms. Thermo-mechanical model was developed to investigate the impact of processing and temperature cycling on the mechanical and delamination stresses induced in the structure...
This paper describes the thermo-mechanical design of an advanced zero-level capping technology used for packaging of a MEMS die. The package approach uses Intermetallic Compound (IMC) bonding to seal the MEMS die with a cap, and uses Through Silicon Via's (TSV) to provide the electrical connections from the MEMS die to the second level substrate (LTCC or PCB). Advanced FEM based thermo-mechanical...
An integrated fluidic system has been fabricated, capable of separating a mixture of different bio-molecules into its components. It is composed of a filter and an actuator; the pressure generated by the actuator sustains the flow of the mixture through the filter. The actuator is made by stacking several layers of conductive polymer. Actuator strain in excess of 10% has been obtained, which corresponds...
This paper reports on the feasibility of parylene N as a dielectric material for through silicon vias (TSV). TSV are the key enabling technology for 3D wafer laver packaging. Parylene is used as an insulating material in one of the approaches adopted for realizing 3D wafer level packaging at IMEC. This paper discusses main issues regarding the processing of parylene N for the TSV application. First,...
Lithographic patterning inside through Si vias (TSV) requires conformal coating of resist over high topography and exposure with a large gap distance. This paper investigates some parameters that have an effect on the resist pattern definition at the bottom of ~100 mum deep via. The influences of the large gap exposure, resist thickness and resist type to the dimension of resist patterns have been...
The integration of through-substrate vias on 100 mum thick high-resistivity silicon (HRSi) wafers within the thin-film multi-chip module technology (MCM-D) is demonstrated in this paper. High quality integrated lumped elements such as thin-film resistors, capacitors and inductors are demonstrated on a microstrip configuration within an MCM-D technology. Microstrip lines integrated on the thin HRSi...
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