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Multi-FPGA systems (MFS) are indispensable for emulating multi-million gates integrated circuits (ICs) for the purpose of functional design verification before IC fabrication. However, with every new generation of FPGAs, the ratio between the logic capacity and the number of inputs and outputs is also increasing. Consequently, the limited FPGA input/output (I/O) pins impose a constraint when the number...
This paper uses the Altera SDK for OpenCL (AOCL) High-Level Synthesis (HLS) tool to accelerate the computation of the SHA-1 hash function. Using FPGAs to increase throughput of this algorithm has been a popular topic in research. The work done thus far, focuses on HDL based design methodologies. The goal of this paper is to determine if the HLS implementation can compare in terms of speed to the HDL...
Multi-FPGA systems (MFSs) are used as custom computing machines, logic emulators and rapid prototyping vehicles. A key aspect of these systems is their programmable routing architecture which is the manner in which wires, FPGAs and Field-Programmable Interconnect Devices (FPIDs) are connected. Several routing architectures for MFSs have been proposed [Arno92] [Butt92] [Hauc94] [Apti96] [Vuil96] [Babb97]...
This paper presents a comprehensive survey of five most widely used in-vehicle networks from three perspectives: system cost, data transmission capacity, and fault-tolerance capability. The paper reviews the pros and cons of each network, and identifies possible approaches to improve the quality of service (QoS). In addition, two classifications of automotive gateways have been presented along with...
Currently, FPGAs serve as Field-Programmable-Systems-on-Chip (FPSoCs) and are widely used to implement computationally intensive real world applications. As the number of components in FPSoCs increase, the interconnect schemes based on Network-on-Chip (NoC) approach are increasingly being used to overcome the deficiencies of the traditional bus- based and point-to-point interconnect schemes. The router...
In this paper, we propose a simplified Log-MAP algorithm that is equivalent to the Log-MAP algorithm in terms of the bit-error-rate (BER) performance, but without its implementation difficulties. The proposed algorithm is based on a linear approximation of the correction function in the Log-MAP algorithm over different signal-to-noise ratio (SNR) regions. This approximation is simple to implement...
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