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This paper presents a compact wideband amplifier at 160 GHz in 40-nm CMOS. Typical wideband amplifier design requires higher-order matching networks and more gain stages, both of which demand larger die area. The presented 8-stage amplifier uses a compact “fishbone” layout technique, and its core size is as small as 190 × 123 µm2. A small-signal gain of 15 dB at 160 GHz and a 3-dB bandwidth of 41...
This paper presents a wideband LC-based VCO using a divide-by-fractional-N injection-locked frequency divider (ILFD), and the fractional-N division is realized by the proposed modulated injection technique. The feedback modulation of incident signals eliminates unwanted injections, which contributes to enlarge the locking range. The ILFD consists of a 2-stage differential ring oscillator, which achieves...
This paper presents a LC-based sub-harmonic injection-locked frequency quadrupler which multiplies a 15 GHz input to 60 GHz quadrature(I/Q) output signals. The proposed quadrupler can use a lower-frequency PLL for incident signal than doublers and triplers, which is very advantageous to implement a wide-tuning and low-phase-noise PLL. The proposed frequency quadrupler is implemented by using a 65...
This paper proposes a novel wideband voltage-controlled oscillator (VCO) for multi-band transceivers. The proposed oscillator has a core VCO and a tuning-range extension circuit, which consists of an injection-locked frequency divider (ILFD), and flip flop dividers. The 2-stage differential ILFD can generate quadrature outputs, and it realizes 2, 3, 4, and 6 of divide ratio with very wide output frequency...
This paper presents a study of design optimization of voltage-controlled oscillators. The phase noise of LC-type oscillators is basically limited by quality factor of inductors. It is experimentally known that higher-Q inductors can be achieved at higher frequencies while oscillation frequency is limited by parasitic capacitances. In this paper, the minimum transistor size and degradation of quality...
This paper proposes a multiple-divide technique using by-2, by-3, and by-4 frequency dividers to realize a lower phase-noise LC-VCO, and explores the design space of low-phase-noise VCO using the multiple-divide technique. In the simulated results using 90-nm CMOS model parameters, the optimum frequency range, achieving better than -191dBc/Hz of FoM, can be extended from 6-12 GHz to 1.5-12 GHz.
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