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In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 ION/IOFF current ratio.
In this paper, we study the thermal characteristics of the bMPI-based 1T-DRAM cell. For a bMPI-FET, it can not only improve the thermal stability about 38% compared with the bPDSOI-FET due to the S/D-tied scheme, but also maintain the desired short-channel characteristics due to the block oxide structure.
The innovative basic punchthrough theory for the unipolar-CMOS is for the first time presented and the first unipolar-CMOS inverter has been fabricated successfully by using the 90nm technology developed in Taiwan National Nano Device Lab. The severe scaling issues with silicon can be further use and no more serious. The low-performance P-FETs can be get rid of and switch much faster both for high-electron-mobility...
In this work, a novel device called dual-channel body-tied (DCBT) MOSFET is proposed. According to numerical simulations, the DCBT MOSFET can reduce the lattice temperature about 51.6% in top and 53.8% in bottom channel, respectively, while maintain the desirable short-channel characteristics, compared with the conventional non-body-tied DC structure.
This paper presents a highly scalable π-shaped source/drain (π-S/D) quasi-silicon-on-insulator (SOI) MOSFET and summarizes its preliminary characteristics compared with the recessed S/D SOI MOSFET and international technology roadmap for semiconductors (ITRS) roadmap values. SiGe-Si epitaxial growth, Si and SiGe etching, growth of epitaxial Si, and selective SiGe removal are used to form the π-S/D...
In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and...
An ultimate n-shaped source/drain (π-S/D) metal-oxide semiconductor (MOS) transistor is proposed in this paper. The method used to fabricate the proposed π-S/D transistor is based on both the classical and modern techniques (such as, Si-SiGe epitaxial growth, selective SiGe removal, etc.) that can be controllable and repeatable. Also, a new and simple process without the need of an additional mask...
This paper proposes two ultimate block oxide (BO) devices called MOS with BO (bMOS) and middle partial insulation with BO (bMPI), respectively. Both he fabrications of the two devices are simple and self-alignment, which help to attain low-cost mass production. The bMOS shows better thermal stability than the bMPI because of its multiple-tie scheme. Also the most conspicuous one is the lattice temperature;...
In this paper, a novel device architecture, namely novel self-align double gate MOSFET with source/drain tie, is proposed and compared with the ITRS. According to the simulation results, our proposed transistor not only enhances the on/off current ratio, but also decreases the drain induced barrier lowering and subthreshold swing due to the double gate scheme structure.
This paper aims to investigate the performance and reliability trade-off of the self-aligned (SA) pi-shaped source/drain (S/D) ultrathin silicon-on-insulator (UTSOI) field-effect transistors (FETs). Based on the simulations, the S/D-tie effects are crucial to the future of quasi-SOI devices. The preliminary results of electrical characteristics of the SA-piFETs are carefully demonstrated.
This paper is to investigate the novel features of a Local Oxidation of silicon multi-tie body polycrystalline silicon thin-film transistor (LOCOS MTB poly-Si TFT) by using numerical simulations. Based on the results, our proposed TFT have improved reliability due to the presence of the LOCOS MTB scheme. Although a multi-body-tied scheme is not compatible in current TFT process, it is believed that...
We present a new vertical sidewall MOSFET with embedded gate (EGVMOS) to reduce the parasitic capacitance which is the major disadvantage in a conventional VMOS. According to simulations, our EGVMOS can not only achieve about 86.34% and 54.76% reduction at Cgd at VDs = 0.05 V and 1.0 V respectively, but also improves the device reliability due to suppressed kink effects, in comparison with a conventional...
In this paper, we propose a novel self-aligned silicon-on-insulator (SOI) MOSFET with Omega-shaped conductive layer and source/drain-tie (SA-OmegaCFET). Based on the TCAD 2D simulation results, we find that combining the applications of a nature Source/Drain (S/D) tie with a recessed S/D region can effectively improve the issue of self-heating effects, but without losing control of the short-channel...
In this work, we present a novel vertical MOSFET with embedded gate structure and try to overcome the challenges mentioned above by modifying the junction depth. Therefore, four types of vertical sidewall MOSFETs with embedded gate (EVGMOS) are also demonstrated and called the EVGMOS having lightly-doped drain (LDD) w/o or w/ 2.5 nm Si etching after gate formation and non-LDD w/o or w/ 2.5 nm Si etching...
In this study, we propose a novel polysilicon thin-film transistor with multi-trenched body (MTB TFT). According to the ISE-TCAD simulations, our proposed MTB TFT gets a steep subthreshold swing (S.S.), a reduced drain-induced barrier lowering (DIBL), a lower drain off-state leakage, and a higher ION/IOFF ration, in comparison with a conventional poly-Si TFT. In addition, due to the MTB scheme, the...
In this paper, we examine the current-voltage (IV) and capacitance-voltage (CV) characteristics of self-aligned (SA), planar block oxide (BO) metal-oxide semiconductor field-effect transistors (MOSFETs) using technology computer-aided design (TCAD) tools. For the first time, a comparison of the different types of BO MOSFETs, such as fully depleted silicon-on-insulator (FDSOI) FET with BO (bFDSOI),...
In this paper, novel FinFET device structures with its bodies been connected together have been for the first time proposed by three-dimensional (3-D) simulation. The short-channel characteristics of threshold voltage (VTH), drain induced barrier lowering (DIBL), and on-off ratio current performance have been examined and explained in this paper. Also, the novel structures show the desired characteristic...
A self-aligned novel S/D tie SOI device is presented for the first time in the field of silicon on insulator technology. The new device having thick-body and body-passway is demonstrated to improve the self-heating effect and decrease the parasitic source/drain resistance. When the source/drain-tie length is too small or too big, the negative differential conductance behavior can be observed. It can...
We demonstrate thermal stability of PTGVMOS (Pseudo Tri-Gate Vertical MOSFET) with native-tie on bulk Si wafer. For comparison three types of structure are designed. According to 2D simulation, our proposed structure show excellent thermal stability, such as the lattice temperature in the drain-on-top configuration and drain-on-bottom configuration were improved 50% and 66.6% respectively. The fabricated...
This paper proposes a new self-aligned process to form the silicon-on-insulator with block oxide. Based on the TCAD simulation, we have proved that the new process can get excellent short-channel effects immunity compared to the previous process [1]. Also, the new process can overcome the problem of the previous one, which can not be used on the thin BOX devices, so that the application of the block...
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