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In this paper, we propose a source-tied vertical MOSFET (STVMOS) by using 3-D simulation. The characteristics of STVMOS are not only similar to the SOI vertical MOSFET (SOI-VMOS), but also have much better thermal reliability. According to TCAD simulation results, we have achieved 70 mV/decade S.S., 145 mV/V DIBL, and more than 109 ION/IOFF current ratio.
This paper presents a highly scalable π-shaped source/drain (π-S/D) quasi-silicon-on-insulator (SOI) MOSFET and summarizes its preliminary characteristics compared with the recessed S/D SOI MOSFET and international technology roadmap for semiconductors (ITRS) roadmap values. SiGe-Si epitaxial growth, Si and SiGe etching, growth of epitaxial Si, and selective SiGe removal are used to form the π-S/D...
In this paper, a non-classical body-tied vertical field-effect transistor (BTVFET) utilizing the self-aligned technique is presented and demonstrated. Based on the simulations, we find out that the electrical characteristics of the BTVFET are better than that of the conventional SOI VFET, including the outstanding ability of heat dissipation, higher channel mobility, lower parasitic capacitance, and...
This paper proposes a new self-aligned process to form the silicon-on-insulator with block oxide. Based on the TCAD simulation, we have proved that the new process can get excellent short-channel effects immunity compared to the previous process [1]. Also, the new process can overcome the problem of the previous one, which can not be used on the thin BOX devices, so that the application of the block...
A non-classical device structure namely self-aligned quasi-silicon-on-insulator (SOI) metal-oxide semiconductor (MOS) field-effect transistor with pi-shaped semiconductor conductive layer (SA-piFET) is presented, seeking to improve the performance and upgrade the reliability of the SOI-based devices. Designed to equip with a SA single crystal silicon channel layer, plus a natural source/drain (S/D)...
This work aims to examine and analyze carefully the effects of block oxide length (LBO) in a 40 nm multi-substrate-contact field-effect transistor (MSCFET). In addition, the proposed structure is based on the self-aligned (SA) gate-to-body technique. In the MSCFET design the two key parameters are the length and the height of the block oxide which are so sensitive to the short-channel effects (SCEs)...
In this paper, the influence of block oxide width (WBO) variations on a newly designed 40-nm gate-length silicon-on-partial-insulator field-effect transistor with block oxide (bSPIFET) was demonstrated and characterized. By utilizing the block oxide (BO) enclosing the sidewall of the Si body, the charge sharing from the source/drain (S/D) regions for a bSPIFET can be significantly reduced. Essentially,...
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