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e-CPI has emerged as a new risk in modern chip design as silicon dies become increasingly thinner and packages become increasingly more complex. e-CPI is different from traditional mechanical reliability related chip-package interaction, as it focuses on package stress impact on electrical circuit performance. A complete e-CPI modeling flow has been demonstrated. Both package FEA models and silicon...
Industrial control system (ICS) plays an important role in the critical infrastructure, and any compromise in their security can result in grave consequences. Since the occurrence of “Stuxnet” event in 2010, the information security problems of ICS cause the intense attentions all over the world. How to assure the security of ICS has become a hot topic in governments, industrial sectors and academic...
Autonomic oscillatory activities exist in almost every living thing and most of them are produced by rhythmic activities of the corresponding neural system. This paper proposes a neural oscillator based on the control of a Schmitt Trigger. The oscillator implements 3 neuron cells and 4 synapse circuits, and integrates them into a compact neural network with a source neuron driving two oscillating...
Reducing interconnect delay and power consumption has become a major concern in deep submicron designs. 3-D technologies have been proposed as a promising solution to mitigate interconnect problems. This paper examines the electrical characterization of vertical intertier connections such as through silicon via (TSV) and microbumps considering process variations and studies their timing impact on...
Simulation circuit design to fulfill the accuracy control of CNG and diesel in internal combustion engine of premixed charge was done firstly. Then simulation research to fulfill the accuracy control of the mixing ratio of CNG and diesel in different working conditions was taken. The result shows the ratio of CNG and diesel can be controlled accurately using the simulation circuit designed by us.
A complete set of analytical gate performance models is developed based on driving current analysis. Closed-form equations for gate delay and output slew are obtained, which capture the dependence on key process and design parameters, such as the input slew, threshold voltage, etc. Using these formulas, gate performance of various topologies is accurately predicted under both nominal and variational...
A drain current model with improved computational efficiency for double-gate (DG) MOSFETs is presented in this paper. Based on our previously proposed potential model, the drain current model is obtained with the implementation of an improved calculation method and the computation efficiency is substantially enhanced. 2-D device simulation (TCAD) is extended to verify the proposed model. In addition,...
A new methodology to bridge package and silicon domain simulations is demonstrated using a new data file to facilitate stress information exchange. The flow integration uses equivalent stress conditions to replace sensitive process information and parameterized modules to minimize user interventions for 3D IC stress simulations.
Strained Si is implemented into the standard CMOS process to enhance carrier transport properties since the 90 nm technology node. However, due to the non-uniform stress distribution in the channel, the enhancement of carrier mobility and threshold voltage strongly depend on layout parameters, such as channel length (L) and source/drain diffusion length (Lsd). In this work, a compact model that physically...
Strain technology has been successfully integrated into CMOS fabrication to improve carrier transport properties since 90 nm node. Due to the non-uniform stress distribution in the channel, the enhancement in carrier mobility, velocity, and threshold voltage shift strongly depend on circuit layout, leading to systematic performance variations among transistors. A compact stress model that physically...
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