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In this paper we consider two software-based control-flow error recovery methods with a rollback recovery mechanism for using in multithreaded architectures. Disregarding to thread interactions between different threads by previous CFE recovery techniques caused these methods not be suitable in multithreaded architectures. Furthermore, the high memory and performance overheads of these techniques...
Fault tree analysis is a widespread-use approach for analyzing reliability and safety in critical systems. In this paper, a new approach is introduced to analyze fault trees based on stochastic logic. Applying stochastic logic makes it possible to present floating point numbers as bit streams, in which the quantity of `1' bits is proportional to the evaluated number. In addition, using stochastic...
This paper proposes two efficient software techniques, Control-flow and Data Errors Correction using Data-flow Graph Consideration (CDCC) and Miniaturized Check-Pointing (MCP), to detect and correct control-flow errors. These techniques have been implemented based on addition of redundant codes in a given program. The creativity applied in the methods for online detection and correction of the control-flow...
Current-day embedded systems are very vulnerable to faults and defects. Anomaly detection is often the primary means of providing early indication of faults and defects. This paper presents a probabilistic method, which employs the probability of data events to evaluate the behavior of system. In order to measure the probability of events in the system, sampling of two events with distinct distance...
This paper presents an analysis of the effects and propagations of transient faults by simulation-based fault injection into the ZPU processor. This analysis is done by injecting 5800 transient faults into the main components of ZPU processor that is described in VHDL language. The sensitivity level of various points of ZPU processor such as PC, SP, IR, Controller, and ALU against fault manifestation...
This paper presents Investigation of Transient Fault Effects in an asynchronous NoC router. The experiment is based on simulation-based fault injection method to assess the fault-tolerant behavior of the asynchronous router. The effort has been accomplished by employing fault injector signal (FIS) in 136 targets. 13600 transient and permanent faults have been injected into the CSP-Verilog model of...
Complexity of design and the lack of suitable test methodology are the major obstacles for widespread use of asynchronous circuit in digital circuit design. Template based synthesis of asynchronous circuits is accepted as an effective way to decrease the complexity of design. However, test frameworks such as fault simulator for synchronous circuits are not applicable for template based asynchronous...
This paper presents an intrinsically verifiable library of quasi delay insensitive asynchronous templates providing an efficient debugging platform for large asynchronous circuits. We proposed using state transition graph to determining necessary properties which must be checked. For every template of a pre-charged full buffer library, we defined PSL properties which are used as monitors verifying...
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